| blib/lib/Verilog/VCD.pm | |||
|---|---|---|---|
| Criterion | Covered | Total | % |
| condition | 12 | 12 | 100.0 |
| line | !l | l&&!r | l&&r | condition |
|---|---|---|---|---|
| 116 | 79 | 8 | 16 | $type eq 'port' and $size ne '1' |
| 143 | 14 | 4 | 2 | $num_sigs > 1 and $use_stdout |
| line | l | !l&&r | !l&&!r | condition |
|---|---|---|---|---|
| 124 | 5 | 58 | 40 | exists $usigs{$full_name} or $all_sigs |
| 161 | 126 | 24 | 131 | / ^ ([01zx]) (.+) /xi or / ^ [br] (\S+) \s+ (.+) /xi |