File Coverage

blib/lib/Verilog/VCD/Writer.pm
Criterion Covered Total %
statement 55 55 100.0
branch 6 8 75.0
condition n/a
subroutine 15 15 100.0
pod 6 6 100.0
total 82 84 97.6


line stmt bran cond sub pod time code
1 2     2   181153 use strict;
  2         4  
  2         54  
2 2     2   9 use warnings;
  2         4  
  2         88  
3             package Verilog::VCD::Writer;
4             $Verilog::VCD::Writer::VERSION = '0.002';
5 2     2   1412 use DateTime;
  2         948893  
  2         98  
6 2     2   1272 use Verilog::VCD::Writer::Module;
  2         11  
  2         85  
7              
8             # ABSTRACT: VCD waveform File creation module.
9            
10              
11              
12 2     2   36 use v5.10;
  2         7  
13 2     2   11 use Moose;
  2         4  
  2         15  
14 2     2   13964 use namespace::clean;
  2         5  
  2         17  
15              
16              
17             has timescale =>(is =>'ro',default=>'1ps');
18             has vcdfile =>(is =>'ro');
19             has date =>(is=>'ro',isa=>'DateTime',default=>sub{DateTime->now()});
20             has _modules=>(is=>'ro',isa=>'ArrayRef[Verilog::VCD::Writer::Module]',
21             default=>sub{[]},
22             traits=>['Array'],
23             handles=>{modules_push=>'push',
24             modules_all=>'elements'}
25             );
26             has _comments=>(is=>'ro',isa=>'ArrayRef',
27             default=>sub{[]},
28             traits=>['Array'],
29             handles=>{comments_push=>'push',
30             comments_all=>'elements'}
31             );
32             has _fh=>(is=>'ro',lazy=>1,builder=>"_redirectSTDOUT");
33              
34             sub _redirectSTDOUT{
35 2     2   5 my $self=shift;
36 2         4 my $fh;
37 2 100       57 if(defined $self->vcdfile){
38 1 50       27 open($fh, ">", $self->vcdfile) or die "unable to write to $self->vcdfile";
39             }else{
40 1 50       9 open($fh, ">-") or die "unable to write to STDOUT";
41             }
42 2         51 return $fh;
43             }
44              
45              
46             sub writeHeaders{
47 2     2 1 1289 my $self=shift;
48 2         60 my $fh=$self->_fh;
49 2         61 say $fh '$date';
50 2         59 say $fh $self->date;
51 2         97 say $fh '$end
52             $version
53             Perl VCD Writer Version '.$Verilog::VCD::Writer::VERSION.'
54             $end
55             $comment';
56 2         93 say $fh join("::\n",$self->comments_all);
57 2         53 say $fh '$end
58             $timescale '.$self->timescale.' $end';
59 2         69 $_->printScope($fh) foreach ($self->modules_all);
60 2         8 say $fh '$enddefinitions $end
61             $dumpvars
62             ';
63             }
64              
65              
66             sub addModule{
67 4     4 1 802 my ($self,$modulename)=@_;
68 4         34 my $m=Verilog::VCD::Writer::Module->new(name=>$modulename,type=>"module");
69 4         2659 $self->modules_push($m);
70 4         13 return $m;
71             }
72              
73              
74              
75             sub setTime {
76 4     4 1 23 my ($self,$time)=@_;
77 4         103 my $fh=$self->_fh;
78 4         15 say $fh '#'.$time;
79            
80             }
81             sub _dec2bin {
82 6     6   38 my $str = unpack("B32", pack("N", shift));
83 6         31 $str =~ s/^0+(?=\d)//; # otherwise you'll get leading zeros
84 6         193 return $str;
85             }
86              
87              
88             sub addValue {
89 12     12 1 67 my ($self,$sig,$value)=@_;
90 12         327 my $fh=$self->_fh;
91             #say STDERR "Adding Values $sig $value";
92 12 100       358 if ($sig->width == 1){
93 6         193 say $fh $value.$sig->symbol;
94             }else {
95 6         26 say $fh "b"._dec2bin($value)." ". $sig->symbol;
96             }
97             }
98              
99              
100             sub addComment{
101 2     2 1 2452 my ($self,$comment)=@_;
102 2         98 $self->comments_push(" ".$comment);
103             }
104              
105              
106             sub flush{
107 2     2 1 1332 my ($self)=shift;
108 2         54 my$fh=$self->_fh;
109 2         26 $fh->autoflush(1);
110              
111             }
112              
113              
114              
115             1;
116              
117             __END__
118              
119             =pod
120              
121             =encoding UTF-8
122              
123             =head1 NAME
124              
125             Verilog::VCD::Writer - VCD waveform File creation module.
126              
127             =head1 VERSION
128              
129             version 0.002
130              
131             =head1 SYNOPSIS
132              
133             use Verilog::VCD::Writer;
134              
135             my $writer=Verilog::VCD::Writer->new(timescale=>'1 ns',vcdfile=>"test.vcd");
136             $writer->addComment("Author:Vijayvithal");
137              
138             my $top=$writer->addModule("top"); # Create toplevel module
139             my $TX=$writer->addSignal("TX",7,0); #Add Signals to top
140             my $RX=$writer->addSignal("RX",7,0);
141              
142             my $dut=$top->addModule("DUT"); Create SubModule
143             $dut->dupSignal($TX,"TX",7,0); #Duplicate signals from Top in submodule
144             $dut->dupSignal($RX,"RX",7,0);
145            
146             $writer->writeHeaders(); # Output the VCD Header.
147             $writer->setTime(0); # Time 0
148             $writer->addValue($TX,0); # Record Transition
149             $writer->addValue($RX,0);
150             $writer->setTime(5); # Time 1ns
151             $writer->addValue($TX,1);
152             $writer->addValue($RX,0);
153              
154             =head1 METHODS
155              
156             =head2 addComment(comment)
157              
158             Adds a comment to the VCD file header. This method should be called before writeHeaders();
159              
160             =head2 flush()
161              
162             Flushes the output buffer.
163              
164             =head1 DESCRIPTION
165             This module originated out of my need to view the <Time,Voltage> CSV dump from the scope using GTKWave.
166              
167             This module provides an interface for creating a VCD (Value change Dump) file.
168              
169             =head2 new (timescale=>'1ps',vcdfile=>'test.vcd',date=>DateTime->now());
170              
171             The constructor takes the following options
172              
173             =over 4
174              
175             =item *
176              
177             timescale: default is '1ps'
178              
179             =item *
180              
181             vcdfile: default is STDOUT, if a filename is given the VCD output will be written to it.
182              
183             =item *
184              
185             Date: a DateTime object, default is current date.
186              
187             =back
188              
189             =head2 writeHeaders()
190              
191             This method should be called after all the modules and signals are declared.
192             This method outputs the header of the VCD file
193              
194             =head2 addModule(ModuleName)
195              
196             This method takes the module name as an input string and returns the corresponding Verilog::VCD::Writer::Module object.
197              
198             =head2 setTime(time)
199              
200             This module takes the time information as an integer value and writes it out to the VCD file.
201              
202             =head2 addValue(Signal,Value)
203              
204             This method takes two parameters, an Object of the type Verilog::VCD::Writer::Signal and the decimal value of the signal at the current time.
205             This module prints the <Signal,Value> information as a formatted line to the VCD file
206              
207             =head1 AUTHOR
208              
209             Vijayvithal Jahagirdar<jvs@cpan.org>
210              
211             =head1 COPYRIGHT AND LICENSE
212              
213             This software is copyright (c) 2017 by Vijayvithal.
214              
215             This is free software; you can redistribute it and/or modify it under
216             the same terms as the Perl 5 programming language system itself.
217              
218             =cut