| blib/lib/Verilog/VCD/Writer/Module.pm | |||
|---|---|---|---|
| Criterion | Covered | Total | % |
| subroutine | 11 | 11 | 100.0 |
| pod | 3 | 4 | 75.0 |
| line | count | pod | subroutine |
|---|---|---|---|
| 3 | 3 | n/a | BEGIN |
| 4 | 3 | n/a | BEGIN |
| 5 | 3 | n/a | BEGIN |
| 9 | 3 | n/a | BEGIN |
| 10 | 3 | n/a | BEGIN |
| 11 | 3 | n/a | BEGIN |
| 12 | 3 | n/a | BEGIN |
| 35 | 13 | Yes | addSignal |
| 46 | 6 | Yes | dupSignal |
| 59 | 2 | Yes | addSubModule |
| 70 | 7 | No | printScope |