Branch Coverage

blib/lib/Verilog/VCD.pm
Criterion Covered Total %
branch 72 72 100.0


line true false branch
30 2 3 unless (defined $file)
49 2 27 unless (defined $file)
54 22 5 if ($opt)
55 3 19 unless (ref $opt eq 'HASH')
61 3 21 exists $opt->{'only_sigs'} ? :
65 4 20 if (exists $opt->{'siglist'}) { }
67 1 3 unless (%usigs)
76 6 17 exists $opt->{'use_stdout'} ? :
78 2 21 unless open my $fh, '<', $file
86 330 235 if (s/ ^ \s* \$ (\w+) \s+ //x)
90 268 62 if length $_
99 157 173 unless length $lines[-1]
101 20 310 if ($keyword eq 'date') { }
20 290 elsif ($keyword eq 'version') { }
18 272 elsif ($keyword eq 'comment') { }
20 252 elsif ($keyword eq 'timescale') { }
78 174 elsif ($keyword eq 'scope') { }
78 96 elsif ($keyword eq 'upscope') { }
79 17 elsif ($keyword eq 'var') { }
133 49 30 if exists $usigs{$full_name} or $all_sigs
142 2 16 unless ($num_sigs)
143 1 1 if ($all_sigs) { }
152 2 14 if ($num_sigs > 1 and $use_stdout)
157 12 2 unless ($only_sigs)
165 2 297 if (s/ ^ \$ comment \s* //x) { }
17 280 elsif (/ ^ \$ (dump \w+) /x) { }
112 168 elsif (/ ^ [#] (\d+) /x) { }
150 18 elsif (/ ^ ([01zx]) (.+) /xi or / ^ [br] (\S+) \s+ (.+) /xi) { }
168 1 1 if length $_
177 1 1 unless length $lines[-1]
190 114 36 if (exists $data{$code})
191 20 94 if ($use_stdout) { }
216 10 10 if (exists $opt->{'timescale'}) { }
228 9 1 if ($tscale =~ / (\d+) \s* ([a-z]+) /xi) { }
248 8 1 if (exists $mults{$units}) { }
257 7 1 if (exists $mults{$new_units}) { }