Condition Coverage

blib/lib/Verilog/Netlist.pm
Criterion Covered Total %
condition 9 15 60.0


and 3 conditions

line !l l&&!r l&&r condition
220 4 0 3 $_->is_top && !$_->is_libcell

or 3 conditions

line l !l&&r !l&&!r condition
146 0 4 0 $self->{'_modules'}{'$root'} ||= $self->new_module("keyword", "root_module", "name", "\$root", @_)
170 0 0 87 $self->{'remove_defines_without_tick'} or $xsym =~ /^\`/
182 39 6 42 $_[0]{'_modules'}{$_[1]} || $_[0]{'_interfaces'}{$_[1]}
276 10 0 239 not -r $filename or -d $filename