Branch Coverage

blib/lib/Verilog/Netlist/Pin.pm
Criterion Covered Total %
branch 49 76 64.4


line true false branch
49 843 8 if (defined $params{'netname'}) { }
8 0 elsif (defined $params{'pinselects'}) { }
68 5 801 if ($self->nets and $self->port)
70 0 5 unless $net->{'net'}
72 5 0 if ($dir eq 'in') { }
0 0 elsif ($dir eq 'out') { }
0 0 elsif ($dir eq 'inout') { }
91 0 7 unless defined $_[0]->_pinselects
96 0 0 unless defined $nets
97 0 0 unless @{$nets;}[0]
103 800 151 unless defined $_[0]->_nets
107 0 0 unless defined $_[0]->_nets
111 0 154 unless defined $_[0]->_pinselects
131 51 53 unless ($self->_nets)
132 51 0 if ($self->_pinselects)
136 30 22 unless defined $net
140 3 19 if (defined $pinselect->msb) { }
153 59 45 unless ($self->port)
154 51 8 if (my $submod = $self->submod)
156 34 17 if ($portname and not $self->cell->byorder) { }
163 17 0 if $self->port
168 45 10 if ($change and $self->_nets and $self->port)
171 0 18 unless $net->{'net'}
172 14 4 if ($dir eq 'in') { }
4 0 elsif ($dir eq 'out') { }
0 0 elsif ($dir eq 'inout') { }
194 0 40 if (not $self->port and $self->submod)
197 17 23 if ($self->port and $self->nets)
198 0 17 unless ($self->type_match)
206 11 6 unless $net->{'net'} and $net->{'net'}->port
209 0 6 if ($netdir eq "in" and $portdir eq "out")
224 34 3 if ($self->port) { }
3 0 elsif ($self->pinnamed) { }
232 1 36 if ($net_cnt >= 2) { }
36 0 elsif ($net_cnt == 1) { }
255 1 39 $net_cnt > 1 ? :
263 37 3 if ($self->port)
267 0 18 unless $net->{'net'}