Branch Coverage

blib/lib/Verilog/EditFiles.pm
Criterion Covered Total %
branch 52 88 59.0


line true false branch
39 0 2 if $Verilog::EditFiles::Debug
40 0 2 if $Verilog::EditFiles::Debug
58 1 0 if $self->{'verbose'}
59 0 1 unless my $fh = "IO::File"->new("<$filename")
73 26 0 if ($self->{'translate_synthesis'})
75 26 0 if $define eq 1
78 0 26 if ($line =~ /(ambit|synopsys|synthesis)\s*translate/)
84 4 3 if (not $commented and $1 eq '//') { }
1 2 elsif (not $commented and $1 eq '/*') { }
1 1 elsif ($commented and $1 eq '*/') { }
93 3 23 if (not $commented and $line =~ /^\s*(module|primitive)\s+([A-Za-z0-9_]+)/) { }
2 21 elsif (not $commented and $line =~ /^\s*end(module|primitive)\b/) { }
0 21 elsif (not $commented and $line =~ /^\s*\`timescale\s.*/ and $self->{'timescale_removal'}) { }
2 19 elsif (not $commented and $line =~ /^\s*\`(end)?celldefine\b/ and $self->{'celldefine'}) { }
96 1 2 if ($modname) { }
102 0 1 unless $newmodname eq $modname
104 0 1 if $self->{'debug'}
108 0 2 if $self->{'debug'}
115 1 11 if $oline =~ /`ifdef\b|`include\b/
116 11 1 if (not $gotifdef) { }
122 0 2 if $self->{'include_header'}
123 0 2 if $self->{'timescale_header'}
124 2 0 if $self->{'celldefine'}
125 2 0 if $self->{'lint_header'}
131 0 2 if $self->{'debug'}
132 0 2 unless $modname
134 2 0 if $self->{'celldefine'}
159 0 1 if (not $ever_module)
160 0 0 if $self->{'debug'}
177 0 2 unless $fileref->{'created'}
187 2 0 if $self->{'verbose'}
189 0 2 unless my $fh = "IO::File"->new(">$filename")
201 1 0 if $self->{'verbose'}
203 0 1 unless my $fh = "IO::File"->new(">$params{'filename'}")
207 0 2 if $fileref->{'is_include'}
208 0 2 if $fileref->{'skip_lint'}
227 0 1 unless defined $params{'filename'}
228 0 1 unless ref $params{'cb'}
229 0 1 unless defined $params{'write_filename'}
234 0 1 unless my $fh = "IO::File"->new("<$params{'filename'}")
246 1 0 if ($wholefile ne $origwholefile)
247 1 0 if $params{'verbose'}
251 0 1 unless my $fh = "IO::File"->new(">$params{'write_filename'}")
255 0 1 if $mode