Branch Coverage

blib/lib/Verilog/Netlist/Net.pm
Criterion Covered Total %
branch 33 64 51.5


line true false branch
113 0 12582 if $params{'type'}
137 0 5 unless $_[0]->_used_in
141 0 0 unless $_[0]->_used_out
145 0 0 unless $_[0]->_used_inout
149 0 0 defined $_[0]->SUPER::stored_lsb ? :
154 0 9 if $dt eq 'signed'
155 6 3 if (defined $self->msb and defined $self->lsb) { }
3 0 elsif (my $width = $_Type_Widths{$dt or $self->net_type or $self->decl_type}) { }
166 0 0 if (defined $flag)
167 0 0 if (my $acc = $_Type_Accessors{$flag}) { }
168 0 0 if ($acc eq 'decl_type') { }
0 0 elsif ($acc eq 'net_type') { }
175 0 0 if $dt and $dt eq 'signed'
186 40 97 if (do { $self->_used_out })
192 0 1 if ($self->_used_out > 1 and not $self->array and abs($self->msb - $self->lsb) + 1 < $self->_used_out)
221 69 51 if ($self->port)
222 37 32 if $self->port->direction eq 'in'
223 25 44 if $self->port->direction eq 'out'
224 6 63 if $self->port->direction eq 'inout'
234 57 63 if $self->data_type
236 0 120 if $self->array
237 20 100 if defined $self->value and $self->value ne ''
239 33 87 if defined $self->comment and $self->comment ne ''
241 120 0 wantarray ? :
247 53 103 $self->_used_in ? :
49 107 $self->_used_out ? :
253 56 100 if defined $self->msb
254 31 125 if defined $self->value and $self->value ne ''
262 0 0 if (my $port = $self->port)
268 0 0 unless defined $net->{'net'}
269 0 0 if ($pin->port and $net->{'net'} == $self) { }
0 0 elsif ($self->name eq $net->{'net'}->name) { }