Condition Coverage

blib/lib/Verilog/Netlist/Net.pm
Criterion Covered Total %
condition 32 54 59.2


and 3 conditions

line !l l&&!r l&&r condition
155 3 0 6 defined $self->msb and defined $self->lsb
175 0 0 0 $dt and $dt eq 'signed'
192 39 0 1 $self->_used_out > 1 and not $self->array
39 1 0 $self->_used_out > 1 and not $self->array and abs($self->msb - $self->lsb) + 1 < $self->_used_out
237 2 98 20 defined $self->value and $self->value ne ''
239 87 0 33 defined $self->comment and $self->comment ne ''
254 0 125 31 defined $self->value and $self->value ne ''
269 0 0 0 $pin->port and $net->{'net'} == $self

or 2 conditions

line l !l condition
133 3 43 $_[0]->_used_in || 0
134 1 50 $_[0]->_used_out || 0
135 0 7 $_[0]->_used_inout || 0
246 156 0 shift() || 0
247 156 0 $self->decl_type || ''
50 106 $self->net_type || ''
69 87 $self->data_type || ''
0 156 $self->array || ''
260 0 0 shift() || 0

or 3 conditions

line l !l&&r !l&&!r condition
155 1 1 1 $dt or $self->net_type
2 1 0 $dt or $self->net_type or $self->decl_type
176 0 0 0 $dt || $self->net_type || $self->decl_type
220 40 80 0 $self->net_type || $self->decl_type