| line |
true |
false |
branch |
|
50
|
0 |
0 |
if ($keysvals[0] ne 'type') |
|
89
|
0 |
0 |
if ($invocant =~ /=HASH\(0x/) |
|
94
|
0 |
0 |
if (not $arg && $arg =~ /\n|\s/m) { } |
|
96
|
0 |
0 |
if (not $arg) { } |
|
|
0 |
0 |
elsif (not scalar($arg) =~ /^\*/) { } |
|
105
|
0 |
0 |
if ($filename) |
|
113
|
0 |
0 |
if ($filename) |
|
119
|
0 |
0 |
if ($filename) |
|
132
|
0 |
0 |
if ($filename) |
|
148
|
0 |
0 |
if ($filename) |
|
167
|
0 |
0 |
if ($suffix) { } |
|
168
|
0 |
0 |
if ($suffix eq 'suffix') |
|
197
|
0 |
0 |
if (@pinlist > 1) { } |
|
220
|
0 |
0 |
if ($suffix) { } |
|
221
|
0 |
0 |
if ($suffix eq 'suffix') |
|
249
|
0 |
0 |
if (@pinlist > 1) { } |
|
273
|
0 |
0 |
if ($line =~ /$pattern/) |
|
289
|
0 |
0 |
if ($line =~ /$pattern.*$pattern/) |
|
296
|
0 |
0 |
if (@result > 1) { } |
|
308
|
0 |
0 |
if (scalar($netlist) =~ /=HASH\(0x/) |
|
312
|
0 |
0 |
unless ($netlist) |
|
316
|
0 |
0 |
if ($netlist) { } |
|
325
|
0 |
0 |
if (scalar($netlist) =~ /=HASH\(0x/) |
|
329
|
0 |
0 |
unless ($netlist) |
|
333
|
0 |
0 |
if (-e "${netlist}cd") { } |
|
350
|
0 |
0 |
if ($dec - 2 ** $n < 0) { } |
|
377
|
0 |
0 |
if (@nets == 1) { } |
|
391
|
0 |
0 |
if ($fullwidth > $buswidth) |
|
395
|
0 |
0 |
if ($fullwidth < $buswidth) |
|
426
|
0 |
0 |
if (@nets == 1) { } |
|
441
|
0 |
0 |
if ($fullwidth > $buswidth) |
|
445
|
0 |
0 |
if ($fullwidth < $buswidth) |
|
472
|
2 |
0 |
if ($design eq 'Verilog') { } |
|
477
|
0 |
2 |
if ($dir ne 'Objects') |
|
482
|
1 |
1 |
if ($skip eq '') { } |
|
483
|
0 |
1 |
$design ne 'Verilog' ? : |
|
486
|
0 |
1 |
if (@v) |
|
503
|
0 |
1 |
unless ($moduledir =~ /\.\./ or -d "$moduledir") |
|
509
|
6 |
1766 |
if /\s+\&make_module/ |
|
510
|
2 |
1764 |
if /\s+\&create_objtest_code/ |
|
511
|
2 |
1762 |
if (/\s+\&create_code_template/) |
|
530
|
4 |
1758 |
if (/use\ strict;/) |
|
540
|
0 |
2 |
if $obj =~ /R_/ |
|
541
|
1 |
1 |
if ($obj ne "$skip.pl") |
|
549
|
1 |
23 |
if (/^sub/) |
|
550
|
24 |
0 |
if ($ok == 1) |
|
566
|
1 |
0 |
if ($design eq 'Verilog') |
|
570
|
0 |
1 |
if ($dir ne 'Objects') |
|
615
|
0 |
0 |
if ($design eq 'Verilog') |
|
619
|
0 |
0 |
if ($dir ne 'Objects') |