Condition Coverage

blib/lib/SystemC/Vregs/Bit.pm
Criterion Covered Total %
condition 23 52 44.2


and 3 conditions

line !l l&&!r l&&r condition
71 0 5 0 $self and $other
103 24 0 0 $lang and lc $lang ne 'verilog'
208 0 0 24 defined $field and $field =~ /^[0-9wbdh]/
254 267 264 3 $thirtytwo and 31 == $bit % 32
301 0 0 0 $overlaps and $overlaps ne 'allowed'
335 24 0 0 $$bitref{'rst'} =~ /^FW/ and $$bitref{'access'} =~ /W/

or 2 conditions

line l !l condition
435 0 0 shift() || \*STDOUT
436 0 0 shift() || ' '

or 3 conditions

line l !l&&r !l&&!r condition
77 0 0 0 $self->ignore or $other->ignore
101 0 0 24 SystemC::Vregs::Language::is_keyword(lc $field) || $SystemC::Vregs::Bit::Keywords{lc $field} && 'Vregs'
112 0 0 24 not defined $field or $field eq ''
139 1 0 23 $field eq 'R' or $field eq 'RO'
22 0 1 $field eq 'RW' or $field eq 'R/W'
0 0 1 $field eq 'W' or $field eq 'WO'
162 16 0 2 $field =~ /^x$/i or $field =~ m[^N/A$]i
254 96 0 534 $bit != $lastbit - 1 or $thirtytwo and 31 == $bit % 32
3 3 528 $bit != $lastbit - 1 or $thirtytwo and 31 == $bit % 32 or $bit == -1
367 314 0 79 $rst eq 'X' or $rst =~ /^FW/