Branch Coverage

blib/lib/SystemC/Vregs/Bit.pm
Criterion Covered Total %
branch 87 176 49.4


line true false branch
42 0 24 unless $$self{'typeref'}
50 0 0 if ($$self{'typeref'})
63 0 0 if defined $$self{'attributes'}{$attr}
71 0 5 unless $self and $other
72 0 5 if lc $$self{'overlaps'} eq 'allowed'
73 0 5 if lc $$other{'overlaps'} eq 'allowed'
74 0 5 if lc $$self{'name'} eq lc $$other{'name'}
75 5 0 if lc $$self{'overlaps'} eq lc $$other{'name'}
76 0 0 if lc $$other{'overlaps'} eq lc $$self{'name'}
77 0 0 if $self->ignore or $other->ignore
83 3 21 if $$self{'desc'} =~ /\boverlaps\s+([a-zA-Z0-9_]+)/i
85 0 24 unless $$self{'desc'}
93 0 24 if ($$self{'typeref'}->attribute_value('allowunder')) { }
94 0 0 unless $field =~ /^[A-Z][A-Za-z0-9_]*$/
97 0 24 unless $field =~ /^[A-Z][A-Za-z0-9]*$/
103 0 24 if ($lang and lc $lang ne 'verilog')
112 0 24 if (not defined $field or $field eq '')
113 0 0 if ($$self{'bits'} =~ /:/) { }
114 0 0 if ($$self{'numbits'} > 64) { }
0 0 elsif ($$self{'numbits'} > 32) { }
127 9 15 unless $field =~ /^(bool|uint\d+_t)$/
138 0 24 if $field =~ s/L//g
139 1 23 if ($field eq 'R' or $field eq 'RO') { }
22 1 elsif ($field eq 'RW' or $field eq 'R/W') { }
0 1 elsif ($field eq 'W' or $field eq 'WO') { }
149 0 24 unless ($field =~ /$SystemC::Vregs::Bit_Access_Regexp/o)
162 6 18 if ($field =~ /^0?x?[0-9a-f_]+$/i) { }
0 18 elsif ($field =~ /^FW-?0$/i) { }
0 18 elsif ($field =~ /^0-?FW$/i) { }
0 18 elsif ($field =~ /^FW-(\(.*\))$/i) { }
16 2 elsif ($field =~ /^x$/i or $field =~ m[^N/A$]i) { }
0 2 elsif ($field =~ /^pin/i) { }
0 2 elsif ($field =~ /^tbd$/i) { }
0 2 elsif ($field eq 'true') { }
0 2 elsif ($field eq 'false') { }
2 0 elsif ($field =~ /^[A-Z0-9_]+$/) { }
182 0 2 if (not $$bitref{'type'}) { }
186 2 0 if ($mnemref)
187 0 2 unless ($mnemref->find_value($field))
208 0 24 unless defined $field and $field =~ /^[0-9wbdh]/
214 17 10 unless $subfield =~ /\[/
217 0 291 if ($busbit =~ /^(b(\d+))\[(\d+)\]$/) { }
0 291 elsif ($busbit =~ /^(h(\d+))\[(\d+)\]$/) { }
291 0 elsif ($busbit =~ /^(w(\d+)|)\[(\d+)\]$/) { }
0 0 elsif ($busbit =~ /^(d(\d+))\[(\d+)\]$/) { }
219 0 0 if $byte
223 0 0 if $byte
227 65 226 if $word
231 0 0 if $word
241 0 24 unless $numbits
254 6 528 if ($bit != $lastbit - 1 or $thirtytwo and 31 == $bit % 32 or $bit == -1)
258 54 48 if ($msb >= 0)
267 24 24 if $thirtytwo
268 24 24 unless $thirtytwo
276 24 0 unless $$bitref{'expand'}
278 0 0 if $SystemC::Vregs::Debug
280 0 0 unless ($ityperef)
293 0 0 unless defined $basebit
299 0 0 if $SystemC::Vregs::Debug
301 0 0 if $overlaps and $overlaps ne 'allowed'
311 0 0 if $overlaps
326 0 24 $access =~ /L/ ? :
327 24 0 $access =~ /R/ ? :
328 0 24 $access =~ /R[^W]*S/ ? :
329 1 23 $access =~ /H/ ? :
330 22 2 $access =~ /W/ ? :
331 0 24 $access =~ /(W[^R]*S|W1C)/ ? :
332 0 24 $access =~ /(W1)/ ? :
335 0 24 if $$bitref{'rst'} =~ /^FW/ and $$bitref{'access'} =~ /W/
344 0 29 unless my $typeref = shift()
347 0 29 if $$bitref{'access_last'}
348 29 0 if $$bitref{'access_read'}
349 0 29 if $$bitref{'access_read_side'}
350 0 29 if $$bitref{'access_write_side'}
357 5 388 if ($prevuser)
359 0 5 unless ($bitref->is_overlap_ok($prevuser))
367 314 79 if ($rst eq 'X' or $rst =~ /^FW/) { }
70 9 elsif ($rst eq '0') { }
0 9 elsif ($rst =~ /^0x[0-9a-f_]+$/i) { }
1 8 elsif ($rst =~ /^[0-9_]+$/i) { }
8 0 elsif ($rst =~ /^[A-Z][A-Z0-9_]*$/) { }
376 0 0 $value & 1 << $bitsleft ? :
381 1 0 $value & 1 << $bitsleft ? :
385 0 8 unless $mnemref
386 8 0 if ($mnemref)
388 0 8 unless ($vref)
392 2 6 if $$vref{'rst_val'} & 1 << $bitsleft
426 0 0 if (&$test_cb($self))