Subroutine Coverage

blib/lib/CPU/Emulator/Z80.pm
Criterion Covered Total %
subroutine 131 134 97.7
pod 12 12 100.0


line count pod subroutine
3 15 n/a BEGIN
4 15 n/a BEGIN
6 15 n/a BEGIN
14 15 n/a BEGIN
15 15 n/a BEGIN
16 15 n/a BEGIN
17 15 n/a BEGIN
18 15 n/a BEGIN
20 15 n/a BEGIN
21 15 n/a BEGIN
22 15 n/a BEGIN
23 15 n/a BEGIN
24 15 n/a BEGIN
25 15 n/a BEGIN
26 15 n/a BEGIN
102 1314 Yes new
140 0 n/a __ANON__
141 0 n/a __ANON__
142 0 n/a __ANON__
189 9191 n/a _derive_register16
192 7972 n/a __ANON__
196 7838 n/a __ANON__
205 10504 n/a _derive_register8
208 653 n/a __ANON__
214 505 n/a __ANON__
238 27 Yes add_input_device
246 42 n/a _get_from_input
266 10 Yes add_output_device
274 21 n/a _put_to_output
290 14971 Yes memory
304 128904 Yes register
316 3 Yes status
328 1 n/a _status_load
350 2 Yes registers
359 1283 Yes format_registers
727 2 Yes nmi
733 3 Yes interrupt
742 11 n/a _interrupts_enabled
748 1346 Yes run
777 2 Yes stopped
783 4997 n/a _fetch
820 3392 n/a _execute
842 19983 n/a _got_prefix
847 312 n/a _check_cond
861 20 n/a _ADD_r16_r16
870 4 n/a _ADC_r16_r16
872 15 n/a _ADC_r8_r8
874 30 n/a _ADD_r8_r8
880 192 n/a _RES
881 193 n/a _SET
883 385 n/a _RES_SET
912 200 n/a _BIT
934 301 n/a _binop
960 15 n/a _AND_r8_r8
961 271 n/a _OR_r8_r8
962 15 n/a _XOR_r8_r8
963 15 n/a _SBC_r8_r8
964 4 n/a _SBC_r16_r16
966 67 n/a _SUB_r8_r8
974 4 n/a _SUB_r16_r16
981 29 n/a _CP_r8_r8
994 276 n/a _DEC
1009 1 n/a _EXX
1016 268 n/a _DJNZ
1033 1 n/a _HALT
1035 21 n/a _INC
1041 26 n/a _LDI
1055 16 n/a _LDIR
1061 9 n/a _LDD
1069 8 n/a _LDDR
1075 14 n/a _CPI
1092 4 n/a _CPIR
1099 9 n/a _CPD
1106 8 n/a _CPDR
1112 1 n/a _RLD
1128 1 n/a _RRD
1144 134 n/a _JR_unconditional
1151 156 n/a _JP_unconditional
1154 19 n/a _CALL_unconditional
1158 8 n/a _LD_ind_r16
1162 22 n/a _LD_ind_r8
1166 681 n/a _LD_indHL_r8
1171 28 n/a _LD_indr16_r8
1176 189 n/a _LD_r16_imm
1181 299 n/a _LD_r8_imm
1188 8 n/a _LD_r16_ind
1192 28 n/a _LD_r8_indr16
1196 22 n/a _LD_r8_ind
1200 590 n/a _LD_r8_indHL
1205 9 n/a _LD_r16_r16
1209 774 n/a _LD_r8_r8
1233 1 n/a _LD_A_R
1234 1 n/a _LD_A_I
1236 2 n/a _LD_A_IR
1248 8 n/a _NEG
1253 282 n/a _NOP
1255 25 n/a _RLCA
1267 25 n/a _RRCA
1279 25 n/a _RLA
1290 25 n/a _RRA
1304 96 n/a _cb_rot
1330 24 n/a _RLC
1334 24 n/a _RRC
1338 24 n/a _RL
1349 24 n/a _RR
1358 24 n/a _SLA
1386 24 n/a _SLL
1416 24 n/a _SRA
1450 24 n/a _SRL
1486 2 n/a _DAA
1529 1 n/a _CPL
1537 4 n/a _SCF
1547 1 n/a _CCF
1557 30 n/a _POP
1564 32 n/a _PUSH
1572 8 n/a _IN_A_n
1578 30 n/a _IN_r_C
1592 1 n/a _OUT_n_A
1599 8 n/a _OUT_C_r
1606 1 n/a _OUT_C_0
1611 3 n/a _IND
1617 3 n/a _INI
1624 2 n/a _INDR
1630 2 n/a _INIR
1636 4 n/a _OUTD
1645 4 n/a _OUTI
1654 3 n/a _OTDR
1660 3 n/a _OTIR
1666 8 n/a _IM
1669 1 n/a _RETI
1672 7 n/a _RETN
1677 5 n/a _DI
1681 3 n/a _EI
1685 1636 n/a _swap_regs