File Coverage

blib/lib/HiPi/Constant.pm
Criterion Covered Total %
statement 36 36 100.0
branch 2 2 100.0
condition n/a
subroutine 7 7 100.0
pod 0 3 0.0
total 45 48 93.7


line stmt bran cond sub pod time code
1             ##########################################################################################
2             # Distribution : HiPi Modules for Raspberry Pi
3             # File : lib/HiPi/Constant.pm
4             # Description : Constants for HiPi
5             # Copyright : Copyright (c) 2013-2020 Mark Dootson
6             # License : This is free software; you can redistribute it and/or modify it under
7             # the same terms as the Perl 5 programming language system itself.
8             #########################################################################################
9              
10             package HiPi::Constant;
11              
12             #########################################################################################
13 5     5   35 use strict;
  5         10  
  5         484  
14 5     5   25 use warnings;
  5         9  
  5         135  
15 5     5   22 use parent qw( Exporter );
  5         8  
  5         23  
16 5     5   2840 use HiPi::RaspberryPi;
  5         30  
  5         11250  
17              
18             our $VERSION ='0.82';
19              
20             our @EXPORT_OK = ( qw( hipi_export_ok hipi_export_constants hipi_export_tags ) );
21             our %EXPORT_TAGS = ( hipi => \@EXPORT_OK );
22              
23             my $MCP_DAC_RESOLUTION_08 = 0x010;
24             my $MCP_DAC_RESOLUTION_10 = 0x020;
25             my $MCP_DAC_RESOLUTION_12 = 0x030;
26             my $MCP_DAC_DUAL_CHANNEL = 0x001;
27             my $MCP_DAC_CAN_BUFFER = 0x002;
28              
29             my $legacyboard = ( HiPi::RaspberryPi::board_type() == 1 ) ? 1 : 0;
30              
31             my $const = {
32             i2c => {
33             I2C_READMODE_SYSTEM => 0,
34             I2C_READMODE_REPEATED_START => 1,
35             I2C_READMODE_START_STOP => 2,
36            
37             I2C_SCANMODE_AUTO => 0,
38             I2C_SCANMODE_QUICK => 1,
39             I2C_SCANMODE_READ => 2,
40            
41             I2C_RETRIES => 0x0701,
42             I2C_TIMEOUT => 0x0702,
43             I2C_SLAVE => 0x0703,
44             I2C_TENBIT => 0x0704,
45             I2C_FUNCS => 0x0705,
46             I2C_SLAVE_FORCE => 0x0706,
47             I2C_RDWR => 0x0707,
48             I2C_PEC => 0x0708,
49             I2C_SMBUS => 0x0720,
50            
51             I2C_M_TEN => 0x0010,
52             I2C_M_RD => 0x0001,
53             I2C_M_NOSTART => 0x4000,
54             I2C_M_REV_DIR_ADDR => 0x2000,
55             I2C_M_IGNORE_NAK => 0x1000,
56             I2C_M_NO_RD_ACK => 0x0800,
57             I2C_M_RECV_LEN => 0x0400,
58            
59             I2C0_SDA => ( $legacyboard ) ? 0 : 28,
60             I2C0_SCL => ( $legacyboard ) ? 1 : 29,
61             I2C1_SDA => 2,
62             I2C1_SCL => 3,
63             I2C_SDA => ( $legacyboard ) ? 0 : 2,
64             I2C_SCL => ( $legacyboard ) ? 1 : 3,
65             ID_SD => 0,
66             ID_SC => 1,
67             },
68            
69             rpi => {
70            
71            
72            
73             RPI_PIN_3 => ( $legacyboard ) ? 0 : 2,
74             RPI_PIN_5 => ( $legacyboard ) ? 1 : 3,
75             RPI_PIN_7 => 4,
76             RPI_PIN_8 => 14,
77             RPI_PIN_10 => 15,
78             RPI_PIN_11 => 17,
79             RPI_PIN_12 => 18,
80             RPI_PIN_13 => 27,
81             RPI_PIN_15 => 22,
82             RPI_PIN_16 => 23,
83             RPI_PIN_18 => 24,
84             RPI_PIN_19 => 10,
85             RPI_PIN_21 => 9,
86             RPI_PIN_22 => 25,
87             RPI_PIN_23 => 11,
88             RPI_PIN_24 => 8,
89             RPI_PIN_26 => 7,
90             RPI_PIN_27 => 0,
91             RPI_PIN_28 => 1,
92             RPI_PIN_29 => 5,
93             RPI_PIN_31 => 6,
94             RPI_PIN_32 => 12,
95             RPI_PIN_33 => 13,
96             RPI_PIN_35 => 19,
97             RPI_PIN_36 => 16,
98             RPI_PIN_37 => 26,
99             RPI_PIN_38 => 20,
100             RPI_PIN_40 => 21,
101            
102             RPI_OUTPUT => 1,
103             RPI_INPUT => 0,
104            
105             RPI_MODE_INPUT => 0,
106             RPI_MODE_OUTPUT => 1,
107             RPI_MODE_ALT0 => 4,
108             RPI_MODE_ALT1 => 5,
109             RPI_MODE_ALT2 => 6,
110             RPI_MODE_ALT3 => 7,
111             RPI_MODE_ALT4 => 3,
112             RPI_MODE_ALT5 => 2,
113            
114             RPI_ALT_FUNCTION_VERSION_2708 => 1,
115             RPI_ALT_FUNCTION_VERSION_2711 => 2,
116            
117             RPI_INT_NONE => 0x00,
118             RPI_INT_FALL => 0x01,
119             RPI_INT_RISE => 0x02,
120             RPI_INT_BOTH => 0x03,
121             RPI_INT_AFALL => 0x04,
122             RPI_INT_ARISE => 0x08,
123             RPI_INT_HIGH => 0x10,
124             RPI_INT_LOW => 0x20,
125            
126             # legacy
127             RPI_PINMODE_INPT => 0,
128             RPI_PINMODE_OUTP => 1,
129             RPI_PINMODE_ALT0 => 4,
130             RPI_PINMODE_ALT1 => 5,
131             RPI_PINMODE_ALT2 => 6,
132             RPI_PINMODE_ALT3 => 7,
133             RPI_PINMODE_ALT4 => 3,
134             RPI_PINMODE_ALT5 => 2,
135            
136             RPI_HIGH => 1,
137             RPI_LOW => 0,
138            
139             RPI_BOARD_TYPE_1 => 1,
140             RPI_BOARD_TYPE_2 => 2,
141             RPI_BOARD_TYPE_3 => 3,
142            
143             RPI_PUD_NULL => -1,
144             RPI_PUD_OFF => 0,
145             RPI_PUD_DOWN => 1,
146             RPI_PUD_UP => 2,
147             RPI_PUD_UNSET => 0x08,
148            
149             RPI_BOARD_REVISION => HiPi::RaspberryPi::board_type(),
150            
151             DEV_GPIO_PIN_STATUS_NONE => 0x00,
152             DEV_GPIO_PIN_STATUS_EXPORTED => 0x01,
153             },
154            
155             spi => {
156             SPI_CPHA => 0x01,
157             SPI_CPOL => 0x02,
158             SPI_MODE_0 => 0x00,
159             SPI_MODE_1 => 0x01,
160             SPI_MODE_2 => 0x02,
161             SPI_MODE_3 => 0x03,
162             SPI_CS_HIGH => 0x04,
163             SPI_LSB_FIRST => 0x08,
164             SPI_3WIRE => 0x10,
165             SPI_LOOP => 0x20,
166             SPI_NO_CS => 0x40,
167             SPI_READY => 0x80,
168             SPI_SPEED_KHZ_500 => 500000,
169             SPI_SPEED_MHZ_1 => 1000000,
170             SPI_SPEED_MHZ_2 => 2000000,
171             SPI_SPEED_MHZ_4 => 4000000,
172             SPI_SPEED_MHZ_8 => 8000000,
173             SPI_SPEED_MHZ_16 => 16000000,
174             SPI_SPEED_MHZ_32 => 32000000,
175             },
176            
177             mcp23x17 => {
178             MCP23S17_A0 => 0x1000,
179             MCP23S17_A1 => 0x1001,
180             MCP23S17_A2 => 0x1002,
181             MCP23S17_A3 => 0x1003,
182             MCP23S17_A4 => 0x1004,
183             MCP23S17_A5 => 0x1005,
184             MCP23S17_A6 => 0x1006,
185             MCP23S17_A7 => 0x1007,
186             MCP23S17_B0 => 0x1010,
187             MCP23S17_B1 => 0x1011,
188             MCP23S17_B2 => 0x1012,
189             MCP23S17_B3 => 0x1013,
190             MCP23S17_B4 => 0x1014,
191             MCP23S17_B5 => 0x1015,
192             MCP23S17_B6 => 0x1016,
193             MCP23S17_B7 => 0x1017,
194            
195             MCP23S17_BANK => 7,
196             MCP23S17_MIRROR => 6,
197             MCP23S17_SEQOP => 5,
198             MCP23S17_DISSLW => 4,
199             MCP23S17_HAEN => 3,
200             MCP23S17_ODR => 2,
201             MCP23S17_INTPOL => 1,
202            
203             MCP23S17_INPUT => 1,
204             MCP23S17_OUTPUT => 0,
205            
206             MCP23S17_HIGH => 1,
207             MCP23S17_LOW => 0,
208            
209             MCP23017_A0 => 0x1000,
210             MCP23017_A1 => 0x1001,
211             MCP23017_A2 => 0x1002,
212             MCP23017_A3 => 0x1003,
213             MCP23017_A4 => 0x1004,
214             MCP23017_A5 => 0x1005,
215             MCP23017_A6 => 0x1006,
216             MCP23017_A7 => 0x1007,
217             MCP23017_B0 => 0x1010,
218             MCP23017_B1 => 0x1011,
219             MCP23017_B2 => 0x1012,
220             MCP23017_B3 => 0x1013,
221             MCP23017_B4 => 0x1014,
222             MCP23017_B5 => 0x1015,
223             MCP23017_B6 => 0x1016,
224             MCP23017_B7 => 0x1017,
225            
226             MCP23017_BANK => 7,
227             MCP23017_MIRROR => 6,
228             MCP23017_SEQOP => 5,
229             MCP23017_DISSLW => 4,
230             MCP23017_HAEN => 3,
231             MCP23017_ODR => 2,
232             MCP23017_INTPOL => 1,
233            
234             MCP23017_INPUT => 1,
235             MCP23017_OUTPUT => 0,
236            
237             MCP23017_HIGH => 1,
238             MCP23017_LOW => 0,
239            
240             MCP_PIN_A0 => 'A0',
241             MCP_PIN_A1 => 'A1',
242             MCP_PIN_A2 => 'A2',
243             MCP_PIN_A3 => 'A3',
244             MCP_PIN_A4 => 'A4',
245             MCP_PIN_A5 => 'A5',
246             MCP_PIN_A6 => 'A6',
247             MCP_PIN_A7 => 'A7',
248             MCP_PIN_B0 => 'B0',
249             MCP_PIN_B1 => 'B1',
250             MCP_PIN_B2 => 'B2',
251             MCP_PIN_B3 => 'B3',
252             MCP_PIN_B4 => 'B4',
253             MCP_PIN_B5 => 'B5',
254             MCP_PIN_B6 => 'B6',
255             MCP_PIN_B7 => 'B7',
256             },
257            
258             mpl3115a2 => {
259             MPL_REG_STATUS => 0x00,
260             MPL_REG_OUT_P_MSB => 0x01,
261             MPL_REG_OUT_P_CSB => 0x02,
262             MPL_REG_OUT_P_LSB => 0x03,
263             MPL_REG_OUT_T_MSB => 0x04,
264             MPL_REG_OUT_T_LSB => 0x05,
265             MPL_REG_DR_STATUS => 0x06,
266             MPL_REG_OUT_P_DELTA_MSB => 0x07,
267             MPL_REG_OUT_P_DELTA_CSB => 0x08,
268             MPL_REG_OUT_P_DELTA_LSB => 0x09,
269             MPL_REG_OUT_T_DELTA_MSB => 0x0A,
270             MPL_REG_OUT_T_DELTA_LSB => 0x0B,
271             MPL_REG_WHO_AM_I => 0x0C,
272             MPL_REG_F_STATUS => 0x0D,
273             MPL_REG_F_DATA => 0x0E,
274             MPL_REG_F_SETUP => 0x0F,
275             MPL_REG_TIME_DLY => 0x10,
276             MPL_REG_SYSMOD => 0x11,
277             MPL_REG_INT_SOURCE => 0x12,
278             MPL_REG_PT_DATA_CFG => 0x13,
279             MPL_REG_BAR_IN_MSB => 0x14,
280             MPL_REG_MAR_IN_LSB => 0x15,
281             MPL_REG_P_TGT_MSB => 0x16,
282             MPL_REG_P_TGT_LSB => 0x17,
283             MPL_REG_T_TGT => 0x18,
284             MPL_REG_P_WND_MSB => 0x19,
285             MPL_REG_P_WND_LSB => 0x1A,
286             MPL_REG_T_WND => 0x1B,
287             MPL_REG_P_MIN_MSB => 0x1C,
288             MPL_REG_P_MIN_CSB => 0x1D,
289             MPL_REG_P_MIN_LSB => 0x1E,
290             MPL_REG_T_MIN_MSB => 0x1F,
291             MPL_REG_T_MIN_LSB => 0x20,
292             MPL_REG_P_MAX_MSB => 0x21,
293             MPL_REG_P_MAX_CSB => 0x22,
294             MPL_REG_P_MAX_LSB => 0x23,
295             MPL_REG_T_MAX_MSB => 0x24,
296             MPL_REG_T_MAX_LSB => 0x25,
297             MPL_REG_CTRL_REG1 => 0x26,
298             MPL_REG_CTRL_REG2 => 0x27,
299             MPL_REG_CTRL_REG3 => 0x28,
300             MPL_REG_CTRL_REG4 => 0x29,
301             MPL_REG_CTRL_REG5 => 0x2A,
302             MPL_REG_OFF_P => 0x2B,
303             MPL_REG_OFF_T => 0x2C,
304             MPL_REG_OFF_H => 0x2D,
305            
306             MPL_CTRL_REG1_SBYB => 0x01,
307             MPL_CTRL_REG1_OST => 0x02,
308             MPL_CTRL_REG1_RST => 0x04,
309             MPL_CTRL_REG1_OS0 => 0x08,
310             MPL_CTRL_REG1_OS1 => 0x10,
311             MPL_CTRL_REG1_OS2 => 0x20,
312             MPL_CTRL_REG1_RAW => 0x40,
313             MPL_CTRL_REG1_ALT => 0x80,
314            
315             MPL_CTRL_REG1_MASK => 0xFF,
316            
317             MPL_CTRL_REG2_ST0 => 0x01,
318             MPL_CTRL_REG2_ST1 => 0x02,
319             MPL_CTRL_REG2_ST2 => 0x04,
320             MPL_CTRL_REG2_ST3 => 0x08,
321             MPL_CTRL_REG2_ALARM_SEL => 0x10,
322             MPL_CTRL_REG2_LOAD_OUTPUT => 0x20,
323            
324             MPL_CTRL_REG2_MASK => 0x3F,
325            
326             MPL_CTRL_REG3_PP_0D2 => 0x01,
327             MPL_CTRL_REG3_IPOL2 => 0x02,
328             MPL_CTRL_REG3_PP_OD1 => 0x10,
329             MPL_CTRL_REG3_IPOL1 => 0x20,
330            
331             MPL_CTRL_REG3_MASK => 0x33,
332            
333             MPL_CTRL_REG4_INT_EN_DRDY => 0x80,
334             MPL_CTRL_REG4_INT_EN_FIFO => 0x40,
335             MPL_CTRL_REG4_INT_EN_PW => 0x20,
336             MPL_CTRL_REG4_INT_EN_TW => 0x10,
337             MPL_CTRL_REG4_INT_EN_PTH => 0x08,
338             MPL_CTRL_REG4_INT_EN_TTH => 0x04,
339             MPL_CTRL_REG4_INT_EN_PCHG => 0x02,
340             MPL_CTRL_REG4_INT_EN_TCHG => 0x01,
341            
342             MPL_CTRL_REG4_MASK => 0xFF,
343            
344             MPL_INTREGS_DRDY => 0x80,
345             MPL_INTREGS_FIFO => 0x40,
346             MPL_INTREGS_PW => 0x20,
347             MPL_INTREGS_TW => 0x10,
348             MPL_INTREGS_PTH => 0x08,
349             MPL_INTREGS_TTH => 0x04,
350             MPL_INTREGS_PCHG => 0x02,
351             MPL_INTREGS_TCHG => 0x01,
352            
353             MPL_INTREGS_MASK => 0xFF,
354            
355             MPL_DR_STATUS_PTOW => 0x80,
356             MPL_DR_STATUS_POW => 0x40,
357             MPL_DR_STATUS_TOW => 0x20,
358             MPL_DR_STATUS_PTDR => 0x08,
359             MPL_DR_STATUS_PDR => 0x04,
360             MPL_DR_STATUS_TDR => 0x02,
361            
362             MPL_DR_STATUS_MASK => 0xEE,
363            
364             MPL_F_STATUS_F_OVF => 0x80,
365             MPL_F_STATUS_F_WMRK_FLAG => 0x40,
366             MPL_F_STATUS_F_CNT5 => 0x20,
367             MPL_F_STATUS_F_CNT4 => 0x10,
368             MPL_F_STATUS_F_CNT3 => 0x08,
369             MPL_F_STATUS_F_CNT2 => 0x04,
370             MPL_F_STATUS_F_CNT1 => 0x02,
371             MPL_F_STATUS_F_CNT0 => 0x01,
372            
373             MPL_F_STATUS_MASK => 0xFF,
374            
375             MPL_PT_DATA_CFG_DREM => 0x04,
376             MPL_PT_DATA_CFG_PDEFE => 0x02,
377             MPL_PT_DATA_CFG_TDEFE => 0x01,
378            
379             MPL_PT_DATA_CFG_MASK => 0x07,
380            
381             MPL_BIT_SBYB => 0,
382             MPL_BIT_OST => 1,
383             MPL_BIT_RST => 2,
384             MPL_BIT_OS0 => 3,
385             MPL_BIT_OS1 => 4,
386             MPL_BIT_OS2 => 5,
387             MPL_BIT_RAW => 6,
388             MPL_BIT_ALT => 7,
389            
390             MPL_BIT_ST0 => 0,
391             MPL_BIT_ST1 => 1,
392             MPL_BIT_ST2 => 2,
393             MPL_BIT_ST3 => 3,
394             MPL_BIT_ALARM_SEL => 4,
395             MPL_BIT_LOAD_OUTPUT => 5,
396            
397             MPL_BIT_PP_0D2 => 0,
398             MPL_BIT_IPOL2 => 1,
399             MPL_BIT_PP_OD1 => 4,
400             MPL_BIT_IPOL1 => 5,
401            
402             # interrupt bits for CTRL_REG5,
403             # INT_SOURCE
404            
405             MPL_BIT_DRDY => 7,
406             MPL_BIT_FIFO => 6,
407             MPL_BIT_PW => 5,
408             MPL_BIT_TW => 4,
409             MPL_BIT_PTH => 3,
410             MPL_BIT_TTH => 2,
411             MPL_BIT_PCHG => 1,
412             MPL_BIT_TCHG => 0,
413            
414             MPL_BIT_PTOW => 7,
415             MPL_BIT_POW => 6,
416             MPL_BIT_TOW => 5,
417             MPL_BIT_PTDR => 3,
418             MPL_BIT_PDR => 2,
419             MPL_BIT_TDR => 1,
420            
421             MPL_BIT_F_OVF => 7,
422             MPL_BIT_F_WMRK_FLAG => 6,
423             MPL_BIT_F_CNT5 => 5,
424             MPL_BIT_F_CNT4 => 4,
425             MPL_BIT_F_CNT3 => 3,
426             MPL_BIT_F_CNT2 => 2,
427             MPL_BIT_F_CNT1 => 1,
428             MPL_BIT_F_CNT0 => 0,
429            
430             MPL_BIT_DREM => 2,
431             MPL_BIT_PDEFE => 1,
432             MPL_BIT_TDEFE => 0,
433            
434            
435             MPL_OSREAD_DELAY => 1060, # left for compatibility with code that uses it.
436            
437             MPL_FUNC_ALTITUDE => 1,
438             MPL_FUNC_PRESSURE => 2,
439             MPL3115A2_ID => 0xC4,
440            
441            
442             MPL_CONTROL_MASK => 0b00111000, #128 oversampling
443             MPL_BYTE_MASK => 0xFF,
444             MPL_WORD_MASK => 0xFFFF,
445            
446             MPL_OVERSAMPLE_1 => 0b00000000,
447             MPL_OVERSAMPLE_2 => 0b00001000,
448             MPL_OVERSAMPLE_4 => 0b00010000,
449             MPL_OVERSAMPLE_8 => 0b00011000,
450             MPL_OVERSAMPLE_16 => 0b00100000,
451             MPL_OVERSAMPLE_32 => 0b00101000,
452             MPL_OVERSAMPLE_64 => 0b00110000,
453             MPL_OVERSAMPLE_128 => 0b00111000,
454            
455             MPL_OVERSAMPLE_MASK => 0b00111000,
456            
457             MPL_BB_I2C_PERI_0 => 0x10,
458             MPL_BB_I2C_PERI_1 => 0x20,
459            
460             },
461            
462             lcd => {
463             HD44780_CLEAR_DISPLAY => 0x01,
464             HD44780_HOME_UNSHIFT => 0x02,
465             HD44780_CURSOR_MODE_LEFT => 0x04,
466             HD44780_CURSOR_MODE_LEFT_SHIFT => 0x05,
467             HD44780_CURSOR_MODE_RIGHT => 0x06,
468             HD44780_CURSOR_MODE_RIGHT_SHIFT => 0x07,
469             HD44780_DISPLAY_OFF => 0x08,
470            
471             HD44780_DISPLAY_ON => 0x0C,
472             HD44780_CURSOR_OFF => 0x0C,
473             HD44780_CURSOR_UNDERLINE => 0x0E,
474             HD44780_CURSOR_BLINK => 0x0F,
475            
476             HD44780_SHIFT_CURSOR_LEFT => 0x10,
477             HD44780_SHIFT_CURSOR_RIGHT => 0x14,
478             HD44780_SHIFT_DISPLAY_LEFT => 0x18,
479             HD44780_SHIFT_DISPLAY_RIGHT => 0x1C,
480            
481             HD44780_CURSOR_POSITION => 0x80,
482            
483             SRX_CURSOR_OFF => 0x0C,
484             SRX_CURSOR_BLINK => 0x0F,
485             SRX_CURSOR_UNDERLINE => 0x0E,
486            
487             HTV2_END_SERIALRX_COMMAND => chr(0xFF),
488            
489             HTV2_BAUD_2400 => 0,
490             HTV2_BAUD_4800 => 1,
491             HTV2_BAUD_9600 => 2,
492             HTV2_BAUD_14400 => 3,
493             HTV2_BAUD_19200 => 4,
494             HTV2_BAUD_28800 => 5,
495             HTV2_BAUD_57600 => 6,
496             HTV2_BAUD_115200 => 7,
497            
498             HTV2_CMD_PRINT => 1,
499             HTV2_CMD_SET_CURSOR_POS => 2,
500             HTV2_CMD_CLEAR_LINE => 3,
501             HTV2_CMD_CLEAR_DISPLAY => 4,
502             HTV2_CMD_LCD_TYPE => 5,
503             HTV2_CMD_HD44780_CMD => 6,
504             HTV2_CMD_BACKLIGHT => 7,
505             HTV2_CMD_WRITE_CHAR => 10,
506             HTV2_CMD_I2C_ADDRESS => 32,
507             HTV2_CMD_BAUD_RATE => 33,
508             HTV2_CMD_CUSTOM_CHAR => 64,
509            
510             SLCD_START_COMMAND => chr(0xFE),
511             SLCD_SPECIAL_COMMAND => chr(0x7C),
512             },
513            
514             hrf69 => {
515             RF69_REG_FIFO => 0x00,
516             RF69_REG_OPMODE => 0x01,
517             RF69_REG_REGDATAMODUL => 0x02,
518             RF69_REG_BITRATEMSB => 0x03,
519             RF69_REG_BITRATELSB => 0x04,
520             RF69_REG_FDEVMSB => 0x05,
521             RF69_REG_FDEVLSB => 0x06,
522             RF69_REG_FRMSB => 0x07,
523             RF69_REG_FRMID => 0x08,
524             RF69_REG_FRLSB => 0x09,
525             RF69_REG_CALLIB => 0x0A,
526             RF69_REG_AFCCTRL => 0x0B,
527             RF69_REG_LISTEN1 => 0x0D,
528             RF69_REG_LISTEN2 => 0x0E,
529             RF69_REG_LISTEN3 => 0x0F,
530             RF69_REG_VERSION => 0x10,
531             RF69_REG_PALEVEL => 0x11,
532             RF69_REG_PARAMP => 0x12,
533             RF69_REG_OCP => 0x13,
534             RF69_REG_LNA => 0x18,
535             RF69_REG_RXBW => 0x19,
536             RF69_REG_AFCBW => 0x1A,
537             RF69_REG_OOKPEAK => 0x1B,
538             RF69_REG_OOKAVG => 0x1C,
539             RF69_REG_OOKFIX => 0x1D,
540             RF69_REG_AFCFEI => 0x1E,
541             RF69_REG_AFCMSB => 0x1F,
542             RF69_REG_AFCLSB => 0x20,
543             RF69_REG_FEIMSB => 0x21,
544             RF69_REG_FEILSB => 0x22,
545             RF69_REG_RSSICONFIG => 0x23,
546             RF69_REG_RSSIVALUE => 0x24,
547             RF69_REG_DIOMAPPING1 => 0x25,
548             RF69_REG_DIOMAPPING2 => 0x26,
549             RF69_REG_IRQFLAGS1 => 0x27,
550             RF69_REG_IRQFLAGS2 => 0x28,
551             RF69_REG_RSSITHRESH => 0x29,
552             RF69_REG_RXTIMEOUT1 => 0x2A,
553             RF69_REG_RXTIMEOUT2 => 0x2B,
554             RF69_REG_PREAMBLEMSB => 0x2C,
555             RF69_REG_PREAMBLELSB => 0x2D,
556             RF69_REG_SYNCCONFIG => 0x2E,
557             RF69_REG_SYNCVALUE1 => 0x2F,
558             RF69_REG_SYNCVALUE2 => 0x30,
559             RF69_REG_SYNCVALUE3 => 0x31,
560             RF69_REG_SYNCVALUE4 => 0x32,
561             RF69_REG_SYNCVALUE5 => 0x33,
562             RF69_REG_SYNCVALUE6 => 0x34,
563             RF69_REG_SYNCVALUE7 => 0x35,
564             RF69_REG_SYNCVALUE8 => 0x36,
565             RF69_REG_PACKETCONFIG1 => 0x37,
566             RF69_REG_PAYLOADLEN => 0x38,
567             RF69_REG_NODEADDRESS => 0x39,
568             RF69_REG_BROADCASTADDRESS => 0x3A,
569             RF69_REG_AUTOMODES => 0x3B,
570             RF69_REG_FIFOTHRESH => 0x3C,
571             RF69_REG_PACKETCONFIG2 => 0x3D,
572             RF69_REG_AESKEY1 => 0x3E,
573             RF69_REG_AESKEY2 => 0x3F,
574             RF69_REG_AESKEY3 => 0x40,
575             RF69_REG_AESKEY4 => 0x41,
576             RF69_REG_AESKEY5 => 0x42,
577             RF69_REG_AESKEY6 => 0x43,
578             RF69_REG_AESKEY7 => 0x44,
579             RF69_REG_AESKEY8 => 0x45,
580             RF69_REG_AESKEY9 => 0x46,
581             RF69_REG_AESKEY10 => 0x47,
582             RF69_REG_AESKEY11 => 0x48,
583             RF69_REG_AESKEY12 => 0x49,
584             RF69_REG_AESKEY13 => 0x4A,
585             RF69_REG_AESKEY14 => 0x4B,
586             RF69_REG_AESKEY15 => 0x4C,
587             RF69_REG_AESKEY16 => 0x4D,
588             RF69_REG_TEMP1 => 0x4E,
589             RF69_REG_TEMP2 => 0x4F,
590            
591             RF69_REG_TESTLNA => 0x58,
592             RF69_REG_TESTPA1 => 0x5A,
593             RF69_REG_TESTPA2 => 0x5C,
594             RF69_REG_TESTDAGC => 0x6F,
595            
596             RF69_REG_TESTAFC => 0x71,
597            
598             RF69_MASK_REG_WRITE => 0x80,
599            
600             RF69_TRUE => 1,
601             RF69_FALSE => 0,
602            
603             RF69_MASK_OPMODE_SEQOFF => 0x80,
604             RF69_MASK_OPMODE_LISTENON => 0x40,
605             RF69_MASK_OPMODE_LISTENABORT => 0x20,
606             RF69_MASK_OPMODE_RX => 0x10,
607             RF69_MASK_OPMODE_TX => 0x0C,
608             RF69_MASK_OPMODE_FS => 0x08,
609             RF69_MASK_OPMODE_SB => 0x04,
610            
611             RF69_MASK_MODEREADY => 0x80,
612             RF69_MASK_FIFONOTEMPTY => 0x40,
613            
614             RF69_MASK_FIFOLEVEL => 0x20,
615             RF69_MASK_FIFOOVERRUN => 0x10,
616             RF69_MASK_PACKETSENT => 0x08,
617             RF69_MASK_TXREADY => 0x20,
618             RF69_MASK_PACKETMODE => 0x60,
619             RF69_MASK_MODULATION => 0x18,
620             RF69_MASK_PAYLOADRDY => 0x04,
621             RF69_MASK_REGDATAMODUL_FSK => 0x00, # Modulation scheme FSK
622             RF69_MASK_REGDATAMODUL_OOK => 0x08, # Modulation scheme OOK
623            
624             RF69_VAL_AFCCTRLS => 0x00, # standard AFC routine
625             RF69_VAL_AFCCTRLI => 0x20, # improved AFC routine
626             RF69_VAL_LNA50 => 0x08, # LNA input impedance 50 ohms
627             RF69_VAL_LNA50G => 0x0E, # LNA input impedance 50 ohms, LNA gain -> 48db
628             RF69_VAL_LNA200 => 0x88, # LNA input impedance 200 ohms
629             RF69_VAL_RXBW60 => 0x43, # channel filter bandwidth 10kHz -> 60kHz page:26
630             RF69_VAL_RXBW120 => 0x41, # channel filter bandwidth 120kHz
631             RF69_VAL_AFCFEIRX => 0x04, # AFC is performed each time RX mode is entered
632             RF69_VAL_RSSITHRESH220 => 0xDC, # RSSI threshold => 0xE4 -> => 0xDC (220)
633             RF69_VAL_PREAMBLELSB3 => 0x03, # preamble size LSB 3
634             RF69_VAL_PREAMBLELSB5 => 0x05, # preamble size LSB 5
635            
636             RF69_VAL_OCP_OFF => 0x0F,
637             RF69_VAL_OCP_ON => 0x1A, # default
638             RF69_PALEVEL_PA0_ON => 0x80, # Default
639             RF69_PALEVEL_PA0_OFF => 0x00,
640             RF69_PALEVEL_PA1_ON => 0x40,
641             RF69_PALEVEL_PA1_OFF => 0x00, # Default
642             RF69_PALEVEL_PA2_ON => 0x20,
643             RF69_PALEVEL_PA2_OFF => 0x00, # Default
644             },
645            
646             mcp3adc => {
647             # msb = channels, lsb = hsb return value mask - 10 bit = 0x03, 12 bit = 0x0F
648             MCP3004 => 0x0403, # 4 channels, 10 bit
649             MCP3008 => 0x0803, # 8 channels, 10 bit
650             MCP3204 => 0x040F, # 4 channels, 12 bit
651             MCP3208 => 0x080F, # 8 channels, 12 bit
652            
653             MCP3ADC_CHAN_0 => 0b00001000, # single-ended CH0
654             MCP3ADC_CHAN_1 => 0b00001001, # single-ended CH1
655             MCP3ADC_CHAN_2 => 0b00001010, # single-ended CH2
656             MCP3ADC_CHAN_3 => 0b00001011, # single-ended CH3
657             MCP3ADC_CHAN_4 => 0b00001100, # single-ended CH4
658             MCP3ADC_CHAN_5 => 0b00001101, # single-ended CH5
659             MCP3ADC_CHAN_6 => 0b00001110, # single-ended CH6
660             MCP3ADC_CHAN_7 => 0b00001111, # single-ended CH7
661             MCP3ADC_DIFF_0_1 => 0b00000000, # differential +CH0 -CH1
662             MCP3ADC_DIFF_1_0 => 0b00000001, # differential -CH0 +CH1
663             MCP3ADC_DIFF_2_3 => 0b00000010, # differential +CH2 -CH3
664             MCP3ADC_DIFF_3_2 => 0b00000011, # differential -CH2 +CH3
665             MCP3ADC_DIFF_4_5 => 0b00000100, # differential +CH4 -CH5
666             MCP3ADC_DIFF_5_4 => 0b00000101, # differential -CH4 +CH5
667             MCP3ADC_DIFF_6_7 => 0b00000110, # differential +CH6 -CH7
668             MCP3ADC_DIFF_7_6 => 0b00000111, # differential -CH6 +CH7
669            
670             MCP3008_S0 => 0b00001000, # single-ended CH0
671             MCP3008_S1 => 0b00001001, # single-ended CH1
672             MCP3008_S2 => 0b00001010, # single-ended CH2
673             MCP3008_S3 => 0b00001011, # single-ended CH3
674             MCP3008_S4 => 0b00001100, # single-ended CH4
675             MCP3008_S5 => 0b00001101, # single-ended CH5
676             MCP3008_S6 => 0b00001110, # single-ended CH6
677             MCP3008_S7 => 0b00001111, # single-ended CH7
678             MCP3008_DIFF_0_1 => 0b00000000, # differential +CH0 -CH1
679             MCP3008_DIFF_1_0 => 0b00000001, # differential -CH0 +CH1
680             MCP3008_DIFF_2_3 => 0b00000010, # differential +CH2 -CH3
681             MCP3008_DIFF_3_2 => 0b00000011, # differential -CH2 +CH3
682             MCP3008_DIFF_4_5 => 0b00000100, # differential +CH4 -CH5
683             MCP3008_DIFF_5_4 => 0b00000101, # differential -CH4 +CH5
684             MCP3008_DIFF_6_7 => 0b00000110, # differential +CH6 -CH7
685             MCP3008_DIFF_7_6 => 0b00000110, # differential -CH6 +CH7
686            
687             MCP3208_S0 => 0b00001000, # single-ended CH0
688             MCP3208_S1 => 0b00001001, # single-ended CH1
689             MCP3208_S2 => 0b00001010, # single-ended CH2
690             MCP3208_S3 => 0b00001011, # single-ended CH3
691             MCP3208_S4 => 0b00001100, # single-ended CH4
692             MCP3208_S5 => 0b00001101, # single-ended CH5
693             MCP3208_S6 => 0b00001110, # single-ended CH6
694             MCP3208_S7 => 0b00001111, # single-ended CH7
695             MCP3208_DIFF_0_1 => 0b00000000, # differential +CH0 -CH1
696             MCP3208_DIFF_1_0 => 0b00000001, # differential -CH0 +CH1
697             MCP3208_DIFF_2_3 => 0b00000010, # differential +CH2 -CH3
698             MCP3208_DIFF_3_2 => 0b00000011, # differential -CH2 +CH3
699             MCP3208_DIFF_4_5 => 0b00000100, # differential +CH4 -CH5
700             MCP3208_DIFF_5_4 => 0b00000101, # differential -CH4 +CH5
701             MCP3208_DIFF_6_7 => 0b00000110, # differential +CH6 -CH7
702             MCP3208_DIFF_7_6 => 0b00000110, # differential -CH6 +CH7
703            
704             MCP3004_S0 => 0b00001000, # single-ended CH0
705             MCP3004_S1 => 0b00001001, # single-ended CH1
706             MCP3004_S2 => 0b00001010, # single-ended CH2
707             MCP3004_S3 => 0b00001011, # single-ended CH3
708             MCP3004_DIFF_0_1 => 0b00000000, # differential +CH0 -CH1
709             MCP3004_DIFF_1_0 => 0b00000001, # differential -CH0 +CH1
710             MCP3004_DIFF_2_3 => 0b00000010, # differential +CH2 -CH3
711             MCP3004_DIFF_3_2 => 0b00000011, # differential -CH2 +CH3
712            
713             MCP3204_S0 => 0b00001000, # single-ended CH0
714             MCP3204_S1 => 0b00001001, # single-ended CH1
715             MCP3204_S2 => 0b00001010, # single-ended CH2
716             MCP3204_S3 => 0b00001011, # single-ended CH3
717             MCP3204_DIFF_0_1 => 0b00000000, # differential +CH0 -CH1
718             MCP3204_DIFF_1_0 => 0b00000001, # differential -CH0 +CH1
719             MCP3204_DIFF_2_3 => 0b00000010, # differential +CH2 -CH3
720             MCP3204_DIFF_3_2 => 0b00000011, # differential -CH2 +CH3
721            
722             },
723            
724             mcp4dac => {
725             MCP_DAC_RESOLUTION_08 => $MCP_DAC_RESOLUTION_08,
726             MCP_DAC_RESOLUTION_10 => $MCP_DAC_RESOLUTION_10,
727             MCP_DAC_RESOLUTION_12 => $MCP_DAC_RESOLUTION_12,
728             MCP_DAC_CAN_BUFFER => $MCP_DAC_CAN_BUFFER,
729             MCP_DAC_DUAL_CHANNEL => $MCP_DAC_DUAL_CHANNEL,
730            
731             MCP_DAC_CHANNEL_A => 0x00,
732             MCP_DAC_CHANNEL_B => 0x8000,
733             MCP_DAC_BUFFER => 0x4000,
734             MCP_DAC_GAIN => 0x00,
735             MCP_DAC_NO_GAIN => 0x2000,
736             MCP_DAC_LIVE => 0x1000,
737             MCP_DAC_SHUTDOWN => 0x00,
738            
739             MCP4801 => 0x100|$MCP_DAC_RESOLUTION_08,
740             MCP4811 => 0x200|$MCP_DAC_RESOLUTION_10,
741             MCP4821 => 0x300|$MCP_DAC_RESOLUTION_12,
742             MCP4802 => 0x400|$MCP_DAC_RESOLUTION_08|$MCP_DAC_DUAL_CHANNEL,
743             MCP4812 => 0x500|$MCP_DAC_RESOLUTION_10|$MCP_DAC_DUAL_CHANNEL,
744             MCP4822 => 0x600|$MCP_DAC_RESOLUTION_12|$MCP_DAC_DUAL_CHANNEL,
745             MCP4901 => 0x700|$MCP_DAC_RESOLUTION_08|$MCP_DAC_CAN_BUFFER,
746             MCP4911 => 0x800|$MCP_DAC_RESOLUTION_10|$MCP_DAC_CAN_BUFFER,
747             MCP4921 => 0x900|$MCP_DAC_RESOLUTION_12|$MCP_DAC_CAN_BUFFER,
748             MCP4902 => 0xA00|$MCP_DAC_RESOLUTION_08|$MCP_DAC_DUAL_CHANNEL|$MCP_DAC_CAN_BUFFER,
749             MCP4912 => 0xB00|$MCP_DAC_RESOLUTION_10|$MCP_DAC_DUAL_CHANNEL|$MCP_DAC_CAN_BUFFER,
750             MCP4922 => 0xC00|$MCP_DAC_RESOLUTION_12|$MCP_DAC_DUAL_CHANNEL|$MCP_DAC_CAN_BUFFER,
751             },
752            
753             openthings => {
754            
755             OPENTHINGS_MANUFACTURER_ENERGENIE => 0x04,
756             OPENTHINGS_MANUFACTURER_SENTEC => 0x01,
757             OPENTHINGS_MANUFACTURER_HILDERBRAND => 0x02,
758             OPENTHINGS_MANUFACTURER_RASPBERRY => 0x3F,
759            
760             OPENTHINGS_PARAM_ALARM => 0x21,
761             OPENTHINGS_PARAM_DEBUG_OUTPUT => 0x2D,
762             OPENTHINGS_PARAM_IDENTIFY => 0x3F,
763             OPENTHINGS_PARAM_SOURCE_SELECTOR => 0x40,
764             OPENTHINGS_PARAM_WATER_DETECTOR => 0x41,
765             OPENTHINGS_PARAM_GLASS_BREAKAGE => 0x42,
766             OPENTHINGS_PARAM_CLOSURES => 0x43,
767             OPENTHINGS_PARAM_DOOR_BELL => 0x44,
768             OPENTHINGS_PARAM_ENERGY => 0x45,
769             OPENTHINGS_PARAM_FALL_SENSOR => 0x46,
770             OPENTHINGS_PARAM_GAS_VOLUME => 0x47,
771             OPENTHINGS_PARAM_AIR_PRESSURE => 0x48,
772             OPENTHINGS_PARAM_ILLUMINANCE => 0x49,
773             OPENTHINGS_PARAM_LEVEL => 0x4C,
774             OPENTHINGS_PARAM_RAINFALL => 0x4D,
775             OPENTHINGS_PARAM_APPARENT_POWER => 0x50,
776             OPENTHINGS_PARAM_POWER_FACTOR => 0x51,
777             OPENTHINGS_PARAM_REPORT_PERIOD => 0x52,
778             OPENTHINGS_PARAM_SMOKE_DETECTOR => 0x53,
779             OPENTHINGS_PARAM_TIME_AND_DATE => 0x54,
780             OPENTHINGS_PARAM_VIBRATION => 0x56,
781             OPENTHINGS_PARAM_WATER_VOLUME => 0x57,
782             OPENTHINGS_PARAM_WIND_SPEED => 0x58,
783             OPENTHINGS_PARAM_GAS_PRESSURE => 0x61,
784             OPENTHINGS_PARAM_BATTERY_LEVEL => 0x62,
785             OPENTHINGS_PARAM_CO_DETECTOR => 0x63,
786             OPENTHINGS_PARAM_DOOR_SENSOR => 0x64,
787             OPENTHINGS_PARAM_EMERGENCY => 0x65,
788             OPENTHINGS_PARAM_FREQUENCY => 0x66,
789             OPENTHINGS_PARAM_GAS_FLOW_RATE => 0x67,
790             OPENTHINGS_PARAM_RELATIVE_HUMIDITY =>0x68,
791             OPENTHINGS_PARAM_CURRENT => 0x69,
792             OPENTHINGS_PARAM_JOIN => 0x6A,
793             OPENTHINGS_PARAM_LIGHT_LEVEL => 0x6C,
794             OPENTHINGS_PARAM_MOTION_DETECTOR => 0x6D,
795             OPENTHINGS_PARAM_OCCUPANCY => 0x6F,
796             OPENTHINGS_PARAM_REAL_POWER => 0x70,
797             OPENTHINGS_PARAM_REACTIVE_POWER => 0x71,
798             OPENTHINGS_PARAM_ROTATION_SPEED => 0x72,
799             OPENTHINGS_PARAM_SWITCH_STATE => 0x73,
800             OPENTHINGS_PARAM_TEMPERATURE => 0x74,
801             OPENTHINGS_PARAM_VOLTAGE => 0x76,
802             OPENTHINGS_PARAM_WATER_FLOW_RATE => 0x77,
803             OPENTHINGS_PARAM_WATER_PRESSURE => 0x78,
804             OPENTHINGS_PARAM_PHASE_1_POWER => 0x79,
805             OPENTHINGS_PARAM_PHASE_2_POWER => 0x7A,
806             OPENTHINGS_PARAM_PHASE_3_POWER => 0x7B,
807             OPENTHINGS_PARAM_3_PHASE_TOTAL => 0x7C,
808            
809             # from Energenie examples
810             OPENTHINGS_PARAM_TEST => 0xAA,
811             OPENTHINGS_WRITE_MASK => 0x80,
812            
813             OPENTHINGS_UINT => 0x00,
814             OPENTHINGS_UINT_BP4 => 0x10,
815             OPENTHINGS_UINT_BP8 => 0x20,
816             OPENTHINGS_UINT_BP12 => 0x30,
817             OPENTHINGS_UINT_BP16 => 0x40,
818             OPENTHINGS_UINT_BP20 => 0x50,
819             OPENTHINGS_UINT_BP24 => 0x60,
820             OPENTHINGS_CHAR => 0x70,
821             OPENTHINGS_SINT => 0x80,
822             OPENTHINGS_SINT_BP8 => 0x90,
823             OPENTHINGS_SINT_BP16 => 0xA0,
824             OPENTHINGS_SINT_BP24 => 0xB0,
825             OPENTHINGS_ENUMERATION => 0xC0,
826             # D0,E0 RESERVED
827             OPENTHINGS_FLOAT => 0xF0,
828             },
829            
830             energenie => {
831             ENERGENIE_ENER314_DUMMY_GROUP => 0xFFFFFF,
832            
833             ENERGENIE_MANUFACTURER_ID => 0x04,
834            
835             ENERGENIE_PRODUCT_ID_MIHO004 => 0x01,
836             ENERGENIE_PRODUCT_ID_MIHO005 => 0x02,
837             ENERGENIE_PRODUCT_ID_MIHO013 => 0x03,
838             ENERGENIE_PRODUCT_ID_MIHO006 => 0x05,
839            
840             ENERGENIE_PRODUCT_ID_MIHO032 => 0x0C,
841             ENERGENIE_PRODUCT_ID_MIHO033 => 0x0D,
842            
843             ENERGENIE_DEFAULT_CRYPTSEED => 242,
844             ENERGENIE_DEFAULT_CRYPTPIP => 0x0100,
845            
846             ENERGENIE_FIFOTHRESH_FSK => 0x81, # Condition to start packet transmission: at least one byte in FIFO
847             ENERGENIE_FIFOTHRESH_OOK => 0x1E, # Condition to start packet transmission: wait for 30 bytes in FIFO
848             ENERGENIE_TXOOK_REPEAT_RATE => 25,
849             ENERGENIE_MESSAGE_BUF_SIZE => 66,
850             ENERGENIE_MAX_FIFO_SIZE => 66,
851             ENERGENIE_NODEADDRESS01 => 0x01, # Node address used in address filtering
852             ENERGENIE_NODEADDRESS04 => 0x04, # Node address used in address filtering
853             ENERGENIE_FDEVMSB_FSK => 0x01, # frequency deviation 5kHz => 0x0052 -> 30kHz => 0x01EC
854             ENERGENIE_FDEVLSB_FSK => 0xEC, # frequency deviation 5kHz => 0x0052 -> 30kHz => 0x01EC
855             ENERGENIE_FDEVMSB_OOK => 0,
856             ENERGENIE_FDEVLSB_OOK => 0,
857             ENERGENIE_FRMSB_434 => 0x6C, # carrier freq -> 434.3MHz => 0x6C9333
858             ENERGENIE_FRMID_434 => 0x93, # carrier freq -> 434.3MHz => 0x6C9333
859             ENERGENIE_FRLSB_434 => 0x33, # carrier freq -> 434.3MHz => 0x6C9333
860             ENERGENIE_FRMSB_433 => 0x6C, # carrier freq -> 433.92MHz => 0x6C7AE1
861             ENERGENIE_FRMID_433 => 0x7A, # carrier freq -> 433.92MHz => 0x6C7AE1
862             ENERGENIE_FRLSB_433 => 0xE1, # carrier freq -> 433.92MHz => 0x6C7AE1
863             ENERGENIE_SYNCVALUE1_FSK => 0x2D, # 1st byte of Sync word
864             ENERGENIE_SYNCVALUE2_FSK => 0xD4, # 2nd byte of Sync word
865             ENERGENIE_SYNCVALUE1_OOK => 0x80, # 1nd byte of Sync word
866            
867             ENERGENIE_SYNC_SIZE_2 => 0x88, # Size of the Synch word = 2 (SyncSize + 1)
868             ENERGENIE_SYNC_SIZE_4 => 0x98, # Size of the Synch word = 4 (SyncSize + 1)
869            
870             ENERGENIE_PACKETCONFIG1_FSK => 0xA2, # Variable length, Manchester coding, Addr must match NodeAddress
871             ENERGENIE_PACKETCONFIG1_FSK_NOADDR => 0xA0, # Variable length, Manchester coding
872             ENERGENIE_PACKETCONFIG1_OOK => 0, # Fixed length, no Manchester coding
873             ENERGENIE_NODEADDRESS => 0x06, # Node address used in address filtering ( when enabled )
874            
875             ENERGENIE_PAYLOADLEN_OOK => 13 + 8 * 17, # fixed OOK Payload Length
876             },
877            
878             si470n => {
879             SI4701 => 1,
880             SI4702 => 2,
881             SI4703 => 3,
882             },
883            
884             pca9685 => {
885             PCA_9685_SERVOTYPE_DEFAULT => 1,
886             PCA_9685_SERVOTYPE_EXT_1 => 2,
887             PCA_9685_SERVOTYPE_EXT_2 => 3,
888             PCA_9685_SERVOTYPE_SG90 => 4,
889            
890             PCA_9685_SERVO_CHANNEL_MASK => 0x0FFF,
891             PCA_9685_FULL_MASK => 0x1000,
892            
893             PCA_9685_SERVO_DIRECTION_CW => 1,
894             PCA_9685_SERVO_DIRECTION_AC => 2,
895             },
896            
897             oled => { # ic cols rows intf
898             SSD1306_128_X_64_I2C => 0x001 + 0x04 + 0x08 + 0x20,
899             SSD1306_128_X_32_I2C => 0x001 + 0x04 + 0x10 + 0x20,
900            
901             SH1106_128_X_64_I2C => 0x002 + 0x04 + 0x08 + 0x20,
902             SH1106_128_X_32_I2C => 0x002 + 0x04 + 0x10 + 0x20,
903            
904             SSD1306_128_X_64_SPI => 0x001 + 0x04 + 0x08 + 0x40,
905             SSD1306_128_X_32_SPI => 0x001 + 0x04 + 0x10 + 0x40,
906            
907             SH1106_128_X_64_SPI => 0x002 + 0x04 + 0x08 + 0x40,
908             SH1106_128_X_32_SPI => 0x002 + 0x04 + 0x10 + 0x40,
909            
910             SSD1322_128_X_64_SPI => 0x100 + 0x04 + 0x08 + 0x40,
911             SSD1322_256_X_64_SPI => 0x100 + 0x80 + 0x08 + 0x40,
912            
913             },
914            
915             ms5611 => {
916             MS5611_OSR_256 => 0x00, # // ADC OSR=256
917             MS5611_OSR_512 => 0x02, # // ADC OSR=512
918             MS5611_OSR_1024 => 0x04, # // ADC OSR=1024
919             MS5611_OSR_2048 => 0x06, # // ADC OSR=2048
920             MS5611_OSR_4096 => 0x08, # // ADC OSR=4096
921             },
922            
923             tmp102 => {
924             TMP102_CR_0_25HZ => 0,
925             TMP102_CR_1HZ => 1,
926             TMP102_CR_4HZ => 2,
927             TMP102_CR_8HZ => 3,
928            
929             TMP102_FAULTS_1 => 0,
930             TMP102_FAULTS_2 => 1,
931             TMP102_FAULTS_4 => 2,
932             TMP102_FAULTS_6 => 3,
933             },
934            
935             epaper => {
936             EPD_WS_1_54_200_X_200_A => 0x01,
937             EPD_WS_1_54_200_X_200_B => 0x02,
938             EPD_WS_1_54_152_X_152_C => 0x03,
939             EPD_WS_2_13_250_X_122_A => 0x04,
940             EPD_WS_2_13_212_X_104_B => 0x05,
941             EPD_WS_2_90_296_X_128_A => 0x06,
942             EPD_WS_2_90_296_X_128_B => 0x07,
943            
944             EPD_PIMORONI_INKY_PHAT_V2 => 0x80,
945            
946             EPD_ROTATION_0 => 0,
947             EPD_ROTATION_90 => 90,
948             EPD_ROTATION_180 => 180,
949             EPD_ROTATION_270 => 270,
950            
951             EPD_FRAME_BPP_1 => 0x01,
952             EPD_FRAME_BPP_2 => 0x02,
953             EPD_FRAME_TYPE_BLACK => 0x01,
954             EPD_FRAME_TYPE_COLOUR => 0x02,
955             EPD_FRAME_TYPE_COLOR => 0x02,
956             EPD_FRAME_TYPE_WHITE => 0x03,
957             EPD_FRAME_TYPE_UNUSED => 0x04,
958            
959             EPD_BLACK_PEN => 0x01,
960             EPD_COLOUR_PEN => 0x02,
961             EPD_COLOR_PEN => 0x02,
962             EPD_RED_PEN => 0x02,
963             EPD_YELLOW_PEN => 0x02,
964            
965             EPD_UPD_MODE_FIXED => 0x01,
966             EPD_UPD_MODE_FULL => 0x02,
967             EPD_UPD_MODE_PARTIAL => 0x03,
968            
969             EPD_BORDER_FLOAT => 0x00,
970             EPD_BORDER_WHITE => 0x01,
971             EPD_BORDER_BLACK => 0x02,
972             EPD_BORDER_COLOUR => 0x03,
973             EPD_BORDER_COLOR => 0x03,
974             EPD_BORDER_RED => 0x03,
975             EPD_BORDER_YELLOW => 0x03,
976            
977             EPD_BORDER_POR => 0xFF,
978             },
979            
980             fl3730 => {
981             # CONFIGURATION REG 0x00
982             FL3730_SSD_NORMAL => 0b00000000,
983             FL3730_SSD_SHUTDOWN => 0b10000000,
984            
985             FL3730_DM_MATRIX_1 => 0b00000,
986             FL3730_DM_MATRIX_2 => 0b01000,
987             FL3730_DM_MATRIX_BOTH => 0b11000,
988            
989             FL3730_AEN_OFF => 0b000,
990             FL3730_AEN_ON => 0b100,
991            
992             FL3730_ADM_8X8 => 0b00,
993             FL3730_ADM_7X9 => 0b01,
994             FL3730_ADM_6X10 => 0b10,
995             FL3730_ADM_5X11 => 0b11,
996            
997             # LIGHTING EFFECT REG 0x0D
998             FL3730_AGS_0_DB => 0b0000000,
999             FL3730_AGS_3_DB => 0b0010000,
1000             FL3730_AGS_6_DB => 0b0100000,
1001             FL3730_AGS_9_DB => 0b0110000,
1002             FL3730_AGS_12_DB => 0b1000000,
1003             FL3730_AGS_15_DB => 0b1010000,
1004             FL3730_AGS_18_DB => 0b1100000,
1005             FL3730_AGS_M6_DB => 0b1110000,
1006            
1007             FL3730_CS_05_MA => 0b1000,
1008             FL3730_CS_10_MA => 0b1001,
1009             FL3730_CS_15_MA => 0b1010,
1010             FL3730_CS_20_MA => 0b1011,
1011             FL3730_CS_25_MA => 0b1100,
1012             FL3730_CS_30_MA => 0b1101,
1013             FL3730_CS_35_MA => 0b1110,
1014             FL3730_CS_40_MA => 0b0000,
1015             FL3730_CS_45_MA => 0b0001,
1016             FL3730_CS_50_MA => 0b0010,
1017             FL3730_CS_55_MA => 0b0011,
1018             FL3730_CS_60_MA => 0b0100,
1019             FL3730_CS_65_MA => 0b0101,
1020             FL3730_CS_70_MA => 0b0110,
1021             FL3730_CS_75_MA => 0b0111,
1022             },
1023            
1024             max7219 => {
1025             MAX7219_FLAG_FLIPPED => 0x01,
1026             MAX7219_FLAG_MIRROR => 0x02,
1027             MAX7219_FLAG_DECIMAL => 0x04,
1028            
1029             MAX7219_REG_NOOP => 0x00,
1030             MAX7219_REG_DIGIT_0 => 0x01,
1031             MAX7219_REG_DIGIT_1 => 0x02,
1032             MAX7219_REG_DIGIT_2 => 0x03,
1033             MAX7219_REG_DIGIT_3 => 0x04,
1034             MAX7219_REG_DIGIT_4 => 0x05,
1035             MAX7219_REG_DIGIT_5 => 0x06,
1036             MAX7219_REG_DIGIT_6 => 0x07,
1037             MAX7219_REG_DIGIT_7 => 0x08,
1038             MAX7219_REG_DECODE_MODE => 0x09,
1039             MAX7219_REG_INTENSITY => 0x0A,
1040             MAX7219_REG_SCAN_LIMIT => 0x0B,
1041             MAX7219_REG_SHUTDOWN => 0x0C,
1042             MAX7219_REG_TEST => 0x0F,
1043             },
1044            
1045             hilink => {
1046             HILINK_CONNSTATUS_CONNECTING => 900,
1047             HILINK_CONNSTATUS_CONNECTED => 901,
1048             HILINK_CONNSTATUS_DISCONNECTED => 902,
1049             HILINK_CONNSTATUS_DISCONNECTING => 903,
1050             },
1051            
1052             mfrc522 => {
1053             ## MIFARE STATUS CODES
1054             MFRC522_STATUS_OK => 1, #// Success
1055             MFRC522_STATUS_ERROR => 2, #// Error in communication
1056             MFRC522_STATUS_COLLISION => 3, #// Collission detected
1057             MFRC522_STATUS_TIMEOUT => 4, #// Timeout in communication.
1058             MFRC522_STATUS_NO_ROOM => 5, #// A buffer is not big enough.
1059             MFRC522_STATUS_INTERNAL_ERROR => 6, #// Internal error in the code. Should not happen ;-)
1060             MFRC522_STATUS_INVALID => 7, #// Invalid argument.
1061             MFRC522_STATUS_CRC_WRONG => 8, #// The CRC_A does not match
1062            
1063             MFRC522_STATUS_UNSUPPORTED_TYPE => 9,
1064             MFRC522_STATUS_BLOCK_NOT_ALLOWED => 10,
1065             MFRC522_STATUS_BAD_PARAM => 11,
1066            
1067             MFRC522_STATUS_MIFARE_NACK => 0xff, #// A MIFARE PICC responded with NAK.
1068            
1069             ## MF522 MFRC522 error codes.
1070             MFRC522_ERROR_OK => 0, # Everything A-OK.
1071             MFRC522_ERROR_NOTAGERR => 1, # No tag error
1072             MFRC522_ERROR_ERR => 2, # General error
1073              
1074             # MF522 Command word
1075             MFRC522_IDLE => 0x00, # NO action; Cancel the current command
1076             MFRC522_MEM => 0x01, # Store 25 byte into the internal buffer.
1077             MFRC522_GENID => 0x02, # Generates a 10 byte random ID number.
1078             MFRC522_CALCCRC => 0x03, # CRC Calculate or selftest.
1079             MFRC522_TRANSMIT => 0x04, # Transmit data
1080             MFRC522_NOCMDCH => 0x07, # No command change.
1081             MFRC522_RECEIVE => 0x08, # Receive Data
1082             MFRC522_TRANSCEIVE => 0x0C, # Transmit and receive data,
1083             MFRC522_AUTHENT => 0x0E, # Authentication Key
1084             MFRC522_SOFTRESET => 0x0F, # Reset
1085              
1086             # Mifare_One tag command word
1087             MIFARE_REQIDL => 0x26, # find the antenna area does not enter hibernation
1088             MIFARE_REQALL => 0x52, # find all the tags antenna area
1089             MIFARE_ANTICOLL => 0x88, # anti-collision
1090             MIFARE_CASCADE => 0x88, # cascade tag
1091             MIFARE_SELECTTAG => 0x93, # selection tag
1092             MIFARE_SELECT_CL1 => 0x93,
1093             MIFARE_SELECT_CL2 => 0x95,
1094             MIFARE_SELECT_CL3 => 0x97,
1095             MIFARE_AUTHENT1A => 0x60, # authentication key A
1096             MIFARE_AUTHENT1B => 0x61, # authentication key B
1097             MIFARE_READ => 0x30, # Read Block
1098             MIFARE_WRITE => 0xA0, # write block
1099             MIFARE_DECREMENT => 0xC0, # debit
1100             MIFARE_INCREMENT => 0xC1, # recharge
1101             MIFARE_RESTORE => 0xC2, # transfer block data to the buffer
1102             MIFARE_TRANSFER => 0xB0, # save the data in the buffer
1103             MIFARE_HALT => 0x50, # Sleep
1104              
1105              
1106             #------------------ MFRC522 registers---------------
1107             #Page 0:Command and Status
1108             MFRC522_REG_Reserved00 => 0x00,
1109             MFRC522_REG_CommandReg => 0x01,
1110             MFRC522_REG_CommIEnReg => 0x02,
1111             MFRC522_REG_DivIEnReg => 0x03,
1112             MFRC522_REG_CommIrqReg => 0x04,
1113             MFRC522_REG_DivIrqReg => 0x05,
1114             MFRC522_REG_ErrorReg => 0x06,
1115             MFRC522_REG_Status1Reg => 0x07,
1116             MFRC522_REG_Status2Reg => 0x08,
1117             MFRC522_REG_FIFODataReg => 0x09,
1118             MFRC522_REG_FIFOLevelReg => 0x0A,
1119             MFRC522_REG_WaterLevelReg => 0x0B,
1120             MFRC522_REG_ControlReg => 0x0C,
1121             MFRC522_REG_BitFramingReg => 0x0D,
1122             MFRC522_REG_CollReg => 0x0E,
1123             MFRC522_REG_Reserved01 => 0x0F,
1124             #Page 1:Command
1125             MFRC522_REG_Reserved10 => 0x10,
1126             MFRC522_REG_ModeReg => 0x11,
1127             MFRC522_REG_TxModeReg => 0x12,
1128             MFRC522_REG_RxModeReg => 0x13,
1129             MFRC522_REG_TxControlReg => 0x14,
1130             MFRC522_REG_TxAutoReg => 0x15,
1131             MFRC522_REG_TxSelReg => 0x16,
1132             MFRC522_REG_RxSelReg => 0x17,
1133             MFRC522_REG_RxThresholdReg => 0x18,
1134             MFRC522_REG_DemodReg => 0x19,
1135             MFRC522_REG_Reserved11 => 0x1A,
1136             MFRC522_REG_Reserved12 => 0x1B,
1137             MFRC522_REG_MifareReg => 0x1C,
1138             MFRC522_REG_Reserved13 => 0x1D,
1139             MFRC522_REG_Reserved14 => 0x1E,
1140             MFRC522_REG_SerialSpeedReg => 0x1F,
1141             #Page 2:CFG
1142             MFRC522_REG_Reserved20 => 0x20,
1143             MFRC522_REG_CRCResultRegM => 0x21,
1144             MFRC522_REG_CRCResultRegH => 0x21,
1145             MFRC522_REG_CRCResultRegL => 0x22,
1146             MFRC522_REG_Reserved21 => 0x23,
1147             MFRC522_REG_ModWidthReg => 0x24,
1148             MFRC522_REG_Reserved22 => 0x25,
1149             MFRC522_REG_RFCfgReg => 0x26,
1150             MFRC522_REG_GsNReg => 0x27,
1151             MFRC522_REG_CWGsPReg => 0x28,
1152             MFRC522_REG_ModGsPReg => 0x29,
1153             MFRC522_REG_TModeReg => 0x2A,
1154             MFRC522_REG_TPrescalerReg => 0x2B,
1155             MFRC522_REG_TReloadRegH => 0x2C,
1156             MFRC522_REG_TReloadRegL => 0x2D,
1157             MFRC522_REG_TCounterValueRegH => 0x2E,
1158             MFRC522_REG_TCounterValueRegL => 0x2F,
1159             #Page 3:TestRegister
1160             MFRC522_REG_Reserved30 => 0x30,
1161             MFRC522_REG_TestSel1Reg => 0x31,
1162             MFRC522_REG_TestSel2Reg => 0x32,
1163             MFRC522_REG_TestPinEnReg => 0x33,
1164             MFRC522_REG_TestPinValueReg => 0x34,
1165             MFRC522_REG_TestBusReg => 0x35,
1166             MFRC522_REG_AutoTestReg => 0x36,
1167             MFRC522_REG_VersionReg => 0x37,
1168             MFRC522_REG_AnalogTestReg => 0x38,
1169             MFRC522_REG_TestDAC1Reg => 0x39,
1170             MFRC522_REG_TestDAC2Reg => 0x3A,
1171             MFRC522_REG_TestADCReg => 0x3B,
1172             MFRC522_REG_Reserved31 => 0x3C,
1173             MFRC522_REG_Reserved32 => 0x3D,
1174             MFRC522_REG_Reserved33 => 0x3E,
1175             MFRC522_REG_Reserved34 => 0x3F,
1176            
1177             MFRC522_PICC_TYPE_UNKNOWN => 0,
1178             MFRC522_PICC_TYPE_ISO_14443_4 => 1, #// PICC compliant with ISO/IEC 14443-4
1179             MFRC522_PICC_TYPE_ISO_18092 => 2, #// PICC compliant with ISO/IEC 18092 (NFC)
1180             MFRC522_PICC_TYPE_MIFARE_MINI => 3, #// MIFARE Classic protocol, 320 bytes
1181             MFRC522_PICC_TYPE_MIFARE_1K => 4, #// MIFARE Classic protocol, 1KB
1182             MFRC522_PICC_TYPE_MIFARE_4K => 5, #// MIFARE Classic protocol, 4KB
1183             MFRC522_PICC_TYPE_MIFARE_UL => 6, #// MIFARE Ultralight or Ultralight C
1184             MFRC522_PICC_TYPE_MIFARE_PLUS => 7, #// MIFARE Plus
1185             MFRC522_PICC_TYPE_MIFARE_DESFIRE => 8, #// MIFARE DESFire
1186             MFRC522_PICC_TYPE_TNP3XXX => 9, #// Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
1187             MFRC522_PICC_TYPE_NOT_COMPLETE => 0xff, #// SAK indicates UID is not complete.
1188            
1189             MIFARE_MF_ACK => 0xA, #// The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
1190             MIFARE_MF_KEY_SIZE => 6, #// A Mifare Crypto1 key is 6 bytes.
1191            
1192             MFCR522_RXGAIN_18dB => 0x00 << 4, # // 000b - 18 dB, minimum
1193             MFCR522_RXGAIN_23dB => 0x01 << 4, # // 001b - 23 dB
1194             MFCR522_RXGAIN_18dB_2 => 0x02 << 4, # // 010b - 18 dB, it seems 010b is a duplicate for 000b
1195             MFCR522_RXGAIN_23dB_2 => 0x03 << 4, # // 011b - 23 dB, it seems 011b is a duplicate for 001b
1196             MFCR522_RXGAIN_33dB => 0x04 << 4, # // 100b - 33 dB, average, and typical default
1197             MFCR522_RXGAIN_38dB => 0x05 << 4, # // 101b - 38 dB
1198             MFCR522_RXGAIN_43dB => 0x06 << 4, # // 110b - 43 dB
1199             MFCR522_RXGAIN_48dB => 0x07 << 4, # // 111b - 48 dB, maximum
1200             MFCR522_RXGAIN_MIN => 0x00 << 4, # // 000b - 18 dB, minimum, convenience for MFCR522_RXGAIN_18dB
1201             MFCR522_RXGAIN_AVG => 0x04 << 4, # // 100b - 33 dB, average, convenience for MFCR522_RXGAIN_33dB
1202             MFCR522_RXGAIN_MAX => 0x07 << 4 # // 111b - 48 dB, maximum, convenience for MFCR522_RXGAIN_48dB
1203            
1204             },
1205            
1206             bmx280 => {
1207             BM280_REG_CALIB1 => 0x88,
1208            
1209             BM280_REG_ID => 0xD0,
1210             BM280_REG_RESET => 0xE0,
1211            
1212             BM280_REG_CALIB2 => 0xE1, # BME280 only
1213            
1214             BM280_REG_CTRL_HUM => 0xF2, # BME280 only
1215             BM280_REG_STATUS => 0xF3,
1216             BM280_REG_CTRL_MEAS => 0xF4,
1217             BM280_REG_CONFIG => 0xF5,
1218            
1219             BM280_REG_PRESS_MSB => 0xF7,
1220             BM280_REG_PRESS_LSB => 0xF8,
1221             BM280_REG_PRESS_XLSB => 0xF9,
1222             BM280_REG_TEMP_MSB => 0xFA,
1223             BM280_REG_TEMP_LSB => 0xFB,
1224             BM280_REG_TEMP_XLSB => 0xFC,
1225             BM280_REG_HUM_MSB => 0xFD, # BME280 only
1226             BM280_REG_HUM_LSB => 0xFE, # BME280 only
1227            
1228             BM280_VAL_RESET => 0xB6,
1229            
1230             BM280_VAL_BMP_CALIB1LEN => 0x18, # 24
1231             BM280_VAL_BME_CALIB1LEN => 0x19, # 25
1232             BM280_VAL_BME_CALIB2LEN => 0x07, # 7
1233            
1234             BM280_TYPE_BME280 => 0x60,
1235             BM280_TYPE_BMP280 => 0x58,
1236            
1237             BM280_COMP_DIG_T1 => 0,
1238             BM280_COMP_DIG_T2 => 1,
1239             BM280_COMP_DIG_T3 => 2,
1240            
1241             BM280_COMP_DIG_P1 => 3,
1242             BM280_COMP_DIG_P2 => 4,
1243             BM280_COMP_DIG_P3 => 5,
1244             BM280_COMP_DIG_P4 => 6,
1245             BM280_COMP_DIG_P5 => 7,
1246             BM280_COMP_DIG_P6 => 8,
1247             BM280_COMP_DIG_P7 => 9,
1248             BM280_COMP_DIG_P8 => 10,
1249             BM280_COMP_DIG_P9 => 11,
1250            
1251             BM280_COMP_DIG_H1 => 12,
1252             BM280_COMP_DIG_H2 => 13,
1253             BM280_COMP_DIG_H3 => 14,
1254             BM280_COMP_DIG_H4 => 15,
1255             BM280_COMP_DIG_H5 => 16,
1256             BM280_COMP_DIG_H6 => 17,
1257            
1258             BM280_MODE_SLEEP => 0b00,
1259             BM280_MODE_NORMAL => 0b11,
1260             BM280_MODE_FORCED => 0b01,
1261            
1262             BM280_OSRS_SKIP => 0b000,
1263             BM280_OSRS_X1 => 0b001,
1264             BM280_OSRS_X2 => 0b010,
1265             BM280_OSRS_X4 => 0b011,
1266             BM280_OSRS_X8 => 0b100,
1267             BM280_OSRS_X16 => 0b101,
1268            
1269             BM280_FILTER_OFF => 0b000,
1270             BM280_FILTER_2 => 0b001,
1271             BM280_FILTER_4 => 0b010,
1272             BM280_FILTER_8 => 0b011,
1273             BM280_FILTER_16 => 0b100,
1274            
1275             BM280_STANDBY_0 => 0b000,
1276             BM280_BME_STANDBY_10 => 0b110,
1277             BM280_BME_STANDBY_20 => 0b111,
1278             BM280_STANDBY_62 => 0b001,
1279             BM280_STANDBY_125 => 0b010,
1280             BM280_STANDBY_250 => 0b011,
1281             BM280_STANDBY_500 => 0b100,
1282             BM280_STANDBY_1000 => 0b101,
1283             BM280_BMP_STANDBY_1000 => 0b110,
1284             BM280_BMP_STANDBY_2000 => 0b111,
1285            
1286             },
1287             };
1288              
1289             my $tagaliases = {
1290             mcp23x17 => [ qw( mcp23017 mcp23S17 ) ],
1291             rpi => [ qw( raspberry ) ],
1292             fl3730 => [ qw( is31fl3730 )],
1293             bmx280 => [ qw( bmp280 bme280 ) ],
1294             };
1295              
1296             sub hipi_export_ok {
1297 5     5 0 14 my @names = ();
1298 5         37 for my $tag ( keys %$const ) {
1299 110         131 for my $cname ( keys %{$const->{$tag}} ) {
  110         647  
1300 5155         6838 push @names, $cname;
1301             }
1302             }
1303 5         860 return @names;
1304             }
1305              
1306             sub hipi_export_constants {
1307 5     5 0 9 my $constants = {};
1308 5         30 for my $tag ( keys %$const ) {
1309 110         137 for my $cname ( keys %{$const->{$tag}} ) {
  110         651  
1310 5155         7971 $constants->{$cname} = $const->{$tag}->{$cname};
1311             }
1312             }
1313 5         34394 return $constants;
1314             }
1315              
1316             sub hipi_export_tags {
1317 5     5 0 15 my %tags = ();
1318 5         31 for my $tag ( keys %$const ) {
1319 110         152 my @names = ();
1320 110         127 for my $cname ( keys %{$const->{$tag}} ) {
  110         664  
1321 5155         6804 push @names, $cname;
1322             }
1323 110         340 $tags{$tag} = \@names;
1324 110 100       276 if(exists($tagaliases->{$tag})) {
1325 20         32 for my $alias ( @{ $tagaliases->{$tag} } ) {
  20         34  
1326 30         82 $tags{$alias} = \@names;
1327             }
1328             }
1329             }
1330 5         80 return %tags;
1331             }
1332              
1333             1;
1334              
1335             __END__